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Differential D154767

[CSKY][test][NFC] Add more tests of conditional branch and value select
ClosedPublic

Authored by benshi001 on Jul 8 2023, 6:09 AM.

Details

Reviewers
zixuan-wu
Commits
rGeac78fdf68f5: [CSKY][test][NFC] Add tests of conditional branch and value select
Summary

These tests will be optimized with BTSTI32/BTSTI16
in the future.

Diff Detail

Event Timeline

benshi001 created this revision.Jul 8 2023, 6:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 8 2023, 6:09 AM
benshi001 requested review of this revision.Jul 8 2023, 6:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 8 2023, 6:09 AM
Herald added subscribers: llvm-commits, jacquesguan. · View Herald Transcript
benshi001 updated this revision to Diff 538363.Jul 8 2023, 6:09 AM
benshi001 added a parent revision: D153751: [CSKY] Optimize ANDI/ORI to BSETI/BCLRI for specific immediates.
benshi001 added a child revision: D154768: [CSKY] Optimize conditional branch and value select with BTSTI.Jul 8 2023, 6:12 AM
Harbormaster completed remote builds in B243932: Diff 538363.Jul 8 2023, 7:36 AM
benshi001 updated this revision to Diff 545528.Jul 31 2023, 12:33 AM
benshi001 edited parent revisions, added: D153614: [CSKY] Optimize ANDI/ORI to BCLRI/BSETI for specific immediates; removed: D153751: [CSKY] Optimize ANDI/ORI to BSETI/BCLRI for specific immediates.
Harbormaster completed remote builds in B249121: Diff 545528.Jul 31 2023, 2:06 AM
zixuan-wu accepted this revision.Aug 4 2023, 12:17 AM
This revision is now accepted and ready to land.Aug 4 2023, 12:17 AM
Closed by commit rGeac78fdf68f5: [CSKY][test][NFC] Add tests of conditional branch and value select (authored by benshi001). · Explain WhyAug 4 2023, 1:11 AM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGeac78fdf68f5: [CSKY][test][NFC] Add tests of conditional branch and value select.

Revision Contents

PathSize
llvm/
test/
CodeGen/
CSKY/
229 lines
216 lines

Diff 545528

llvm/test/CodeGen/CSKY/br.ll

Show First 20 Lines • Show All 6,605 Lines • ▼ Show 20 Lines
; GENERIC-NEXT: rts16 ; GENERIC-NEXT: rts16
entry: entry:
br i1 %c, label %label1, label %label2 br i1 %c, label %label1, label %label2
label1: label1:
ret i1 1 ret i1 1
label2: label2:
ret i1 0 ret i1 0
} }
define i32 @br_bit_test_eq_0(i32 %c) {
; CHECK-LABEL: br_bit_test_eq_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: bnez32 a0, .LBB145_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
; CHECK-NEXT: .LBB145_2: # %label2
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: br_bit_test_eq_0:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: bt16 .LBB145_2
; GENERIC-NEXT: # %bb.1: # %label1
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
; GENERIC-NEXT: .LBB145_2: # %label2
; GENERIC-NEXT: movi16 a0, 0
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%t0 = and i32 %c, 131072
%t1 = icmp eq i32 %t0, 0
br i1 %t1, label %label1, label %label2
label1:
ret i32 1
label2:
ret i32 0
}
define i32 @br_bit_test_ne_0(i32 %c) {
; CHECK-LABEL: br_bit_test_ne_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: bez32 a0, .LBB146_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
; CHECK-NEXT: .LBB146_2: # %label2
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: br_bit_test_ne_0:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: bf16 .LBB146_2
; GENERIC-NEXT: # %bb.1: # %label1
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
; GENERIC-NEXT: .LBB146_2: # %label2
; GENERIC-NEXT: movi16 a0, 0
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%t0 = and i32 %c, 131072
%t1 = icmp ne i32 %t0, 0
br i1 %t1, label %label1, label %label2
label1:
ret i32 1
label2:
ret i32 0
}
define i32 @br_bit_test_eq_mask(i32 %c) {
; CHECK-LABEL: br_bit_test_eq_mask:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: bez32 a0, .LBB147_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
; CHECK-NEXT: .LBB147_2: # %label2
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: br_bit_test_eq_mask:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: bf16 .LBB147_2
; GENERIC-NEXT: # %bb.1: # %label1
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
; GENERIC-NEXT: .LBB147_2: # %label2
; GENERIC-NEXT: movi16 a0, 0
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%t0 = and i32 %c, 131072
%t1 = icmp eq i32 %t0, 131072
br i1 %t1, label %label1, label %label2
label1:
ret i32 1
label2:
ret i32 0
}
define i32 @br_bit_test_ne_mask(i32 %c) {
; CHECK-LABEL: br_bit_test_ne_mask:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: bnez32 a0, .LBB148_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
; CHECK-NEXT: .LBB148_2: # %label2
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: br_bit_test_ne_mask:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: bt16 .LBB148_2
; GENERIC-NEXT: # %bb.1: # %label1
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
; GENERIC-NEXT: .LBB148_2: # %label2
; GENERIC-NEXT: movi16 a0, 0
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%t0 = and i32 %c, 131072
%t1 = icmp ne i32 %t0, 131072
br i1 %t1, label %label1, label %label2
label1:
ret i32 1
label2:
ret i32 0
}
define i32 @br_lowbit_test_ne_0(i32 %c) {
; CHECK-LABEL: br_lowbit_test_ne_0:
; CHECK: # %bb.0:
; CHECK-NEXT: andi32 a0, a0, 256
; CHECK-NEXT: bez32 a0, .LBB149_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
; CHECK-NEXT: .LBB149_2: # %label2
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: br_lowbit_test_ne_0:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: lsli16 a3, a1, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: movi16 a2, 1
; GENERIC-NEXT: lsli16 a2, a2, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: bf16 .LBB149_2
; GENERIC-NEXT: # %bb.1: # %label1
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
; GENERIC-NEXT: .LBB149_2: # %label2
; GENERIC-NEXT: movi16 a0, 0
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%t0 = and i32 %c, 256
%t1 = icmp ne i32 %t0, 0
br i1 %t1, label %label1, label %label2
label1:
ret i32 1
label2:
ret i32 0
}

llvm/test/CodeGen/CSKY/select.ll

Show First 20 Lines • Show All 8,153 Lines • ▼ Show 20 Lines
; GENERIC-NEXT: .LBB201_2: # %entry ; GENERIC-NEXT: .LBB201_2: # %entry
; GENERIC-NEXT: mov16 a0, a2 ; GENERIC-NEXT: mov16 a0, a2
; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16 ; GENERIC-NEXT: rts16
entry: entry:
%ret = select i1 %c, i1 %m, i1 %n %ret = select i1 %c, i1 %m, i1 %n
ret i1 %ret ret i1 %ret
} }
define i32 @select_bit_test_eq_0(i32 %0) {
; CHECK-LABEL: select_bit_test_eq_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: movi16 a0, 23
; CHECK-NEXT: movi16 a1, 1
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: select_bit_test_eq_0:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: mvcv16 a1
; GENERIC-NEXT: movi16 a0, 1
; GENERIC-NEXT: btsti16 a1, 0
; GENERIC-NEXT: bt16 .LBB200_2
; GENERIC-NEXT: # %bb.1:
; GENERIC-NEXT: movi16 a0, 23
; GENERIC-NEXT: .LBB200_2:
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%2 = and i32 %0, 131072
%3 = icmp eq i32 %2, 0
%4 = select i1 %3, i32 1, i32 23
ret i32 %4
}
define i32 @select_bit_test_ne_0(i32 %0) {
; CHECK-LABEL: select_bit_test_ne_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: movi16 a0, 34
; CHECK-NEXT: movi16 a1, 5
; CHECK-NEXT: movt32 a0, a1
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: select_bit_test_ne_0:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: mvcv16 a0
; GENERIC-NEXT: movi16 a1, 1
; GENERIC-NEXT: subu16 a1, a0
; GENERIC-NEXT: movi16 a0, 5
; GENERIC-NEXT: btsti16 a1, 0
; GENERIC-NEXT: bt16 .LBB201_2
; GENERIC-NEXT: # %bb.1:
; GENERIC-NEXT: movi16 a0, 34
; GENERIC-NEXT: .LBB201_2:
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%2 = and i32 %0, 131072
%3 = icmp ne i32 %2, 0
%4 = select i1 %3, i32 5, i32 34
ret i32 %4
}
define i32 @select_bit_test_eq_mask(i32 %0) {
; CHECK-LABEL: select_bit_test_eq_mask:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: movi16 a0, 5
; CHECK-NEXT: movi16 a1, 34
; CHECK-NEXT: movt32 a0, a1
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: select_bit_test_eq_mask:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: mvcv16 a0
; GENERIC-NEXT: movi16 a1, 1
; GENERIC-NEXT: subu16 a1, a0
; GENERIC-NEXT: movi16 a0, 34
; GENERIC-NEXT: btsti16 a1, 0
; GENERIC-NEXT: bt16 .LBB202_2
; GENERIC-NEXT: # %bb.1:
; GENERIC-NEXT: movi16 a0, 5
; GENERIC-NEXT: .LBB202_2:
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%2 = and i32 %0, 131072
%3 = icmp eq i32 %2, 131072
%4 = select i1 %3, i32 34, i32 5
ret i32 %4
}
define i32 @select_bit_test_ne_mask(i32 %0) {
; CHECK-LABEL: select_bit_test_ne_mask:
; CHECK: # %bb.0:
; CHECK-NEXT: movih32 a1, 2
; CHECK-NEXT: and16 a0, a1
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: movi16 a0, 34
; CHECK-NEXT: movi16 a1, 5
; CHECK-NEXT: movt32 a0, a1
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: select_bit_test_ne_mask:
; GENERIC: # %bb.0:
; GENERIC-NEXT: .cfi_def_cfa_offset 0
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: movi16 a3, 2
; GENERIC-NEXT: lsli16 a3, a3, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: lsli16 a2, a1, 8
; GENERIC-NEXT: or16 a2, a3
; GENERIC-NEXT: or16 a2, a1
; GENERIC-NEXT: and16 a2, a0
; GENERIC-NEXT: cmpnei16 a2, 0
; GENERIC-NEXT: mvcv16 a0
; GENERIC-NEXT: movi16 a1, 1
; GENERIC-NEXT: subu16 a1, a0
; GENERIC-NEXT: movi16 a0, 5
; GENERIC-NEXT: btsti16 a1, 0
; GENERIC-NEXT: bt16 .LBB203_2
; GENERIC-NEXT: # %bb.1:
; GENERIC-NEXT: movi16 a0, 34
; GENERIC-NEXT: .LBB203_2:
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%2 = and i32 %0, 131072
%3 = icmp eq i32 %2, 131072
%4 = select i1 %3, i32 5, i32 34
ret i32 %4
}
define i32 @select_lowbit_test_ne_0(i32 %0) {
; CHECK-LABEL: select_lowbit_test_ne_0:
; CHECK: # %bb.0:
; CHECK-NEXT: andi32 a0, a0, 256
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: movi16 a0, 34
; CHECK-NEXT: movi16 a1, 5
; CHECK-NEXT: movt32 a0, a1
; CHECK-NEXT: rts16
;
; GENERIC-LABEL: select_lowbit_test_ne_0:
; GENERIC: # %bb.0:
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 4
; GENERIC-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
; GENERIC-NEXT: .cfi_offset l0, -4
; GENERIC-NEXT: subi16 sp, sp, 4
; GENERIC-NEXT: .cfi_def_cfa_offset 8
; GENERIC-NEXT: movi16 a1, 0
; GENERIC-NEXT: lsli16 a2, a1, 24
; GENERIC-NEXT: lsli16 a3, a1, 16
; GENERIC-NEXT: or16 a3, a2
; GENERIC-NEXT: movi16 a2, 1
; GENERIC-NEXT: lsli16 l0, a2, 8
; GENERIC-NEXT: or16 l0, a3
; GENERIC-NEXT: or16 l0, a1
; GENERIC-NEXT: and16 l0, a0
; GENERIC-NEXT: cmpnei16 l0, 0
; GENERIC-NEXT: mvcv16 a0
; GENERIC-NEXT: subu16 a2, a0
; GENERIC-NEXT: movi16 a0, 5
; GENERIC-NEXT: btsti16 a2, 0
; GENERIC-NEXT: bt16 .LBB204_2
; GENERIC-NEXT: # %bb.1:
; GENERIC-NEXT: movi16 a0, 34
; GENERIC-NEXT: .LBB204_2:
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
; GENERIC-NEXT: addi16 sp, sp, 4
; GENERIC-NEXT: rts16
%2 = and i32 %0, 256
%3 = icmp ne i32 %2, 0
%4 = select i1 %3, i32 5, i32 34
ret i32 %4
}