[CSKY] Optimize implementation of intrinsic 'llvm.cttz.i32'

[benshi001]

clang/test/CodeGen/CSKY/csky-builtins.c

1 ↗

(On Diff #538356)

This file is pure test, has nothing to do with llvm.cttz, just to avoid another patch.

[benshi001]

ping ...

[zixuan-wu]

clang/test/CodeGen/CSKY/csky-builtins.c

1 ↗

(On Diff #538356)

Don't make unrelated patch together in one single commit.

67 ↗

(On Diff #538356)

Those are target-independent intrinsics/builtins. I think it's no more need to test for specific target such as csky again, unless it's different behavior or output.

llvm/test/CodeGen/CSKY/intrinsic.ll

53

Again. It's related to cttz?

[benshi001]

clang/test/CodeGen/CSKY/csky-builtins.c

67 ↗

(On Diff #538356)

removed.

[benshi001]

llvm/test/CodeGen/CSKY/intrinsic.ll

53

I have made another patch for these additional tests.
https://reviews.llvm.org/D156543

[zixuan-wu]

llvm/test/CodeGen/CSKY/intrinsic.ll

21

I think we can also test the condition that the second argument is zero.

[benshi001]

Closed by

https://reviews.llvm.org/rG80cd505914dfc2f38f57341f9bef9d208fdc238e
https://github.com/llvm/llvm-project/commit/80cd505914dfc2f38f57341f9bef9d208fdc238e

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::UADDO_CARRY, MVT::i32, Legal);
   setOperationAction(ISD::USUBO_CARRY, MVT::i32, Legal);
   setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
 
   setOperationAction(ISD::SREM, MVT::i32, Expand);
   setOperationAction(ISD::UREM, MVT::i32, Expand);
   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
-  setOperationAction(ISD::CTTZ, MVT::i32, Expand);
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
   setOperationAction(ISD::ROTR, MVT::i32, Expand);
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
if (!Subtarget.hasE2()) {
     setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i16, Expand);
     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
   }
 
   if (!Subtarget.has2E3()) {
     setOperationAction(ISD::ABS, MVT::i32, Expand);
     setOperationAction(ISD::BITREVERSE, MVT::i32, Expand);
+    setOperationAction(ISD::CTTZ, MVT::i32, Expand);
     setOperationAction(ISD::SDIV, MVT::i32, Expand);
     setOperationAction(ISD::UDIV, MVT::i32, Expand);
   }
 
   setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
 
   // Float
 

llvm/lib/Target/CSKY/CSKYInstrInfo.td

 
 // Other operations.
 let Predicates = [iHasE2] in {
   def : Pat<(rotl GPR:$rs1, GPR:$rs2),
             (ROTL32 GPR:$rs1, (ANDI32 GPR:$rs2, 0x1f))>;
   let Predicates = [iHas2E3] in {
     def : Pat<(bitreverse GPR:$rx), (BREV32 GPR:$rx)>;
     def : Pat<(bswap GPR:$rx), (REVB32 GPR:$rx)>;
+    def : Pat<(i32 (cttz GPR:$rx)), (FF1 (BREV32 GPR:$rx))>;
   }
   def : Pat<(i32 (ctlz GPR:$rx)), (FF1 GPR:$rx)>;
 }
 
 //===----------------------------------------------------------------------===//
 // Pseudo for assembly
 //===----------------------------------------------------------------------===//
 

llvm/test/CodeGen/CSKY/intrinsic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 -mattr=+2e3 < %s -mtriple=csky | FileCheck %s
 
 define i32 @ctlz(i32 %x) {
 ; CHECK-LABEL: ctlz:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ff1.32 a0, a0
 ; CHECK-NEXT:    rts16
 entry:
   %nlz = call i32 @llvm.ctlz.i32(i32 %x, i1 1)
   ret i32 %nlz
 }
 
+define i32 @cttz_0(i32 %x) {
+; CHECK-LABEL: cttz_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bez32 a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %cond.false
+; CHECK-NEXT:    brev32 a0, a0
+; CHECK-NEXT:    ff1.32 a0, a0
+; CHECK-NEXT:    rts16
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    movi16 a0, 32
+; CHECK-NEXT:    rts16
+entry:
+  %ntz = call i32 @llvm.cttz.i32(i32 %x, i1 0)
+  ret i32 %ntz
+}
+
+define i32 @cttz_1(i32 %x) {
+; CHECK-LABEL: cttz_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    brev32 a0, a0
+; CHECK-NEXT:    ff1.32 a0, a0
+; CHECK-NEXT:    rts16
+entry:
+  %ntz = call i32 @llvm.cttz.i32(i32 %x, i1 1)
+  ret i32 %ntz
+}
+
 define i32 @bswap(i32 %x) {
 ; CHECK-LABEL: bswap:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    revb16 a0, a0
 ; CHECK-NEXT:    rts16
 entry:
   %revb32 = call i32 @llvm.bswap.i32(i32 %x)
   ret i32 %revb32
 }
 
 define i32 @bitreverse(i32 %x) {
 ; CHECK-LABEL: bitreverse:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    brev32 a0, a0
 ; CHECK-NEXT:    rts16
 entry:
   %brev32 = call i32 @llvm.bitreverse.i32(i32 %x)
   ret i32 %brev32
 }
 
 declare i32 @llvm.bswap.i32(i32)
 declare i32 @llvm.ctlz.i32 (i32, i1)
+declare i32 @llvm.cttz.i32 (i32, i1)
 declare i32 @llvm.bitreverse.i32(i32)