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[clang-format] Add Verilog suffixes to the scripts
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Authored by sstwcw on Jul 4 2023, 4:50 PM.

Details

Summary

I decided not to wait for D149088 because it was taking a long time.

The capture group in the regexp was changed to non-capturing. It
doesn't need to be captured.

Diff Detail

Event Timeline

sstwcw created this revision.Jul 4 2023, 4:50 PM
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sstwcw requested review of this revision.Jul 4 2023, 4:50 PM
NOTE: Clang-Format Team Automated Review Comment

It looks like your clang-format review does not contain any unit tests, please try to ensure all code changes have a unit test (unless this is an NFC or refactoring, adding documentation etc..)

Add your unit tests in clang/unittests/Format and you can build with ninja FormatTests. We recommend using the verifyFormat(xxx) format of unit tests rather than EXPECT_EQ as this will ensure you change is tolerant to random whitespace changes (see FormatTest.cpp as an example)

For situations where your change is altering the TokenAnnotator.cpp which can happen if you are trying to improve the annotation phase to ensure we are correctly identifying the type of a token, please add a token annotator test in TokenAnnotatorTest.cpp

This comment was removed by MyDeveloperDay.
This revision is now accepted and ready to land.Jul 6 2023, 12:26 PM
owenpan accepted this revision.Jul 10 2023, 2:18 PM
This revision was landed with ongoing or failed builds.Aug 23 2023, 8:24 PM
This revision was automatically updated to reflect the committed changes.