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Differential D154322

[X86]Precommit test cases for D154193
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Authored by XinWang10 on Jul 2 2023, 10:55 PM.

Details

Reviewers
skan
pengfei
craig.topper
RKSimon
Commits
rGf64e11369f3a: [X86]Precommit test cases for D154193
Summary

Add mir test cases for D154193, which tend to remove test16rr in possible and32ri+test16rr, similar to what we did for and32*+test64rr.

Diff Detail

Event Timeline

XinWang10 created this revision.Jul 2 2023, 10:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 2 2023, 10:55 PM
Herald added a subscriber: pengfei. · View Herald Transcript
XinWang10 requested review of this revision.Jul 2 2023, 10:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 2 2023, 10:55 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
XinWang10 added reviewers: skan, pengfei, craig.topper, RKSimon.Jul 2 2023, 10:57 PM
XinWang10 mentioned this in D154193: [X86]Remove TEST in AND32ri+TEST16rr in peephole-opt.
pengfei accepted this revision.Jul 2 2023, 11:20 PM
This revision is now accepted and ready to land.Jul 2 2023, 11:20 PM
Harbormaster completed remote builds in B242736: Diff 536661.Jul 3 2023, 12:00 AM
Closed by commit rGf64e11369f3a: [X86]Precommit test cases for D154193 (authored by XinWang10). · Explain WhyJul 3 2023, 1:44 AM
This revision was automatically updated to reflect the committed changes.
XinWang10 added a commit: rGf64e11369f3a: [X86]Precommit test cases for D154193.

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
284 lines

Diff 536684

llvm/test/CodeGen/X86/peephole-test-after-add.mir

Show All 32 Lines define void @test_not_erased_when_eflags_change(ptr %0, i64 %1, i64 %2, i64 %3, ptr %4) {
%8 = xor i64 %3, 5 %8 = xor i64 %3, 5
%9 = icmp eq i64 %7, 0 %9 = icmp eq i64 %7, 0
%10 = select i1 %9, i64 %1, i64 %7 %10 = select i1 %9, i64 %1, i64 %7
store i64 %10, ptr %0, align 8 store i64 %10, ptr %0, align 8
store i64 %8, ptr %4, align 8 store i64 %8, ptr %4, align 8
ret void ret void
} }
define i16 @erase_test16(i16 %0, i16 %1, ptr nocapture %2) {
entry:
%3 = icmp ne i16 %0, 0
%4 = and i16 %1, 123
%5 = icmp eq i16 %4, 0
%6 = select i1 %3, i1 %5, i1 false
br i1 %6, label %if.then, label %if.end
if.then: ; preds = %entry
store i16 %0, ptr %2, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i16 0
}
define i16 @erase_test16_bigimm(i16 %0, i32 %1, ptr nocapture %2) {
entry:
%3 = icmp ne i16 %0, 0
%4 = and i32 %1, 123456
%truc = trunc i32 %4 to i16
%5 = icmp eq i16 %truc, 0
%6 = select i1 %3, i1 %5, i1 false
br i1 %6, label %if.then, label %if.end
if.then: ; preds = %entry
store i16 %0, ptr %2, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i16 0
}
... ...
--- ---
name: test_erased name: test_erased
alignment: 16 alignment: 16
tracksDebugUserValues: false tracksDebugUserValues: false
registers: registers:
- { id: 0, class: gr64, preferred-register: '' } - { id: 0, class: gr64, preferred-register: '' }
- { id: 1, class: gr64, preferred-register: '' } - { id: 1, class: gr64, preferred-register: '' }
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines bb.0 (%ir-block.5):
%9:gr64 = XOR64ri8 %3, 5, implicit-def dead $eflags %9:gr64 = XOR64ri8 %3, 5, implicit-def dead $eflags
TEST64rr %8, %8, implicit-def $eflags TEST64rr %8, %8, implicit-def $eflags
%10:gr64 = CMOV64rr %8, %1, 4, implicit $eflags %10:gr64 = CMOV64rr %8, %1, 4, implicit $eflags
MOV64mr %0, 1, $noreg, 0, $noreg, killed %10 :: (store (s64) into %ir.0) MOV64mr %0, 1, $noreg, 0, $noreg, killed %10 :: (store (s64) into %ir.0)
MOV64mr %4, 1, $noreg, 0, $noreg, killed %9 :: (store (s64) into %ir.4) MOV64mr %4, 1, $noreg, 0, $noreg, killed %9 :: (store (s64) into %ir.4)
RET 0 RET 0
... ...
---
name: erase_test16
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
callsEHReturn: false
callsUnwindInit: false
hasEHCatchret: false
hasEHScopes: false
hasEHFunclets: false
isOutlined: false
debugInstrRef: true
failsVerification: false
tracksDebugUserValues: false
registers:
- { id: 0, class: gr32, preferred-register: '' }
- { id: 1, class: gr32, preferred-register: '' }
- { id: 2, class: gr64, preferred-register: '' }
- { id: 3, class: gr16, preferred-register: '' }
- { id: 4, class: gr16, preferred-register: '' }
- { id: 5, class: gr32, preferred-register: '' }
- { id: 6, class: gr32, preferred-register: '' }
- { id: 7, class: gr16, preferred-register: '' }
liveins:
- { reg: '$edi', virtual-reg: '%0' }
- { reg: '$esi', virtual-reg: '%1' }
- { reg: '$rdx', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
functionContext: ''
maxCallFrameSize: 4294967295
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
hasTailCall: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
entry_values: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: erase_test16
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x60000000), %bb.3(0x20000000)
; CHECK-NEXT: liveins: $edi, $esi, $rdx
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdx
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
; CHECK-NEXT: TEST16rr [[COPY3]], [[COPY3]], implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY1]], 123, implicit-def dead $eflags
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY [[AND32ri]].sub_16bit
; CHECK-NEXT: TEST16rr [[COPY4]], [[COPY4]], implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.3, 5, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: MOV16mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s16) into %ir.2, align 4)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr16 = COPY [[MOV32r0_]].sub_16bit
; CHECK-NEXT: $ax = COPY [[COPY5]]
; CHECK-NEXT: RET 0, $ax
bb.0.entry:
successors: %bb.3(0x60000000), %bb.2(0x20000000)
liveins: $edi, $esi, $rdx
%2:gr64 = COPY $rdx
%1:gr32 = COPY $esi
%0:gr32 = COPY $edi
%3:gr16 = COPY %0.sub_16bit
TEST16rr %3, %3, implicit-def $eflags
JCC_1 %bb.2, 4, implicit $eflags
JMP_1 %bb.3
bb.3.entry:
successors: %bb.1(0x55555555), %bb.2(0x2aaaaaab)
%5:gr32 = AND32ri %1, 123, implicit-def dead $eflags
%4:gr16 = COPY %5.sub_16bit
TEST16rr %4, %4, implicit-def $eflags
JCC_1 %bb.2, 5, implicit $eflags
JMP_1 %bb.1
bb.1.if.then:
successors: %bb.2(0x80000000)
MOV16mr %2, 1, $noreg, 0, $noreg, %3 :: (store (s16) into %ir.2, align 4)
bb.2.if.end:
%6:gr32 = MOV32r0 implicit-def dead $eflags
%7:gr16 = COPY %6.sub_16bit
$ax = COPY %7
RET 0, $ax
...
---
name: erase_test16_bigimm
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
callsEHReturn: false
callsUnwindInit: false
hasEHCatchret: false
hasEHScopes: false
hasEHFunclets: false
isOutlined: false
debugInstrRef: true
failsVerification: false
tracksDebugUserValues: false
registers:
- { id: 0, class: gr32, preferred-register: '' }
- { id: 1, class: gr32, preferred-register: '' }
- { id: 2, class: gr64, preferred-register: '' }
- { id: 3, class: gr16, preferred-register: '' }
- { id: 4, class: gr16, preferred-register: '' }
- { id: 5, class: gr32, preferred-register: '' }
- { id: 6, class: gr32, preferred-register: '' }
- { id: 7, class: gr16, preferred-register: '' }
liveins:
- { reg: '$edi', virtual-reg: '%0' }
- { reg: '$esi', virtual-reg: '%1' }
- { reg: '$rdx', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
functionContext: ''
maxCallFrameSize: 4294967295
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
hasTailCall: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
entry_values: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: erase_test16_bigimm
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x60000000), %bb.3(0x20000000)
; CHECK-NEXT: liveins: $edi, $esi, $rdx
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdx
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
; CHECK-NEXT: TEST16rr [[COPY3]], [[COPY3]], implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY1]], 57920, implicit-def dead $eflags
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY [[AND32ri]].sub_16bit
; CHECK-NEXT: TEST16rr [[COPY4]], [[COPY4]], implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.3, 5, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: MOV16mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s16) into %ir.2, align 4)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr16 = COPY [[MOV32r0_]].sub_16bit
; CHECK-NEXT: $ax = COPY [[COPY5]]
; CHECK-NEXT: RET 0, $ax
bb.0.entry:
successors: %bb.3(0x60000000), %bb.2(0x20000000)
liveins: $edi, $esi, $rdx
%2:gr64 = COPY $rdx
%1:gr32 = COPY $esi
%0:gr32 = COPY $edi
%3:gr16 = COPY %0.sub_16bit
TEST16rr %3, %3, implicit-def $eflags
JCC_1 %bb.2, 4, implicit $eflags
JMP_1 %bb.3
bb.3.entry:
successors: %bb.1(0x55555555), %bb.2(0x2aaaaaab)
%5:gr32 = AND32ri %1, 57920, implicit-def dead $eflags
%4:gr16 = COPY %5.sub_16bit
TEST16rr %4, %4, implicit-def $eflags
JCC_1 %bb.2, 5, implicit $eflags
JMP_1 %bb.1
bb.1.if.then:
successors: %bb.2(0x80000000)
MOV16mr %2, 1, $noreg, 0, $noreg, %3 :: (store (s16) into %ir.2, align 4)
bb.2.if.end:
%6:gr32 = MOV32r0 implicit-def dead $eflags
%7:gr16 = COPY %6.sub_16bit
$ax = COPY %7
RET 0, $ax
...