[CSKY] Optimize conditional branch with BHZ32/BHSZ32/BLSZ32/BLZ32

[benshi001]

Summary

Add more Pats which generates BHZ32/BHSZ32/BLSZ32/BLZ32.

[zixuan-wu]

need more case about bhz/bhsz?

[benshi001]

In D153607#4462762, @zixuan-wu wrote:

need more case about bhz/bhsz?

It is hard to add tests for

def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),
          (BHZ32 GPR:$rs1, bb:$imm16)>;

Since the original IR pattern

%icmp = icmp sge i32 %x, 1
br i1 %icmp, label %label1, label %label2

is always transformed to an equivalent form by DAGCombiner

%icmp = icmp slt i32 %x, 1
br i1 %icmp, label %label2, label %label1

before reaching to the CSKY backend.

And BHSZ32 has the same issue.

I add these two Pats for BHSZ32 and BHZ32, just in case there is future changes in the DAGCombiner.

[zixuan-wu]

I think the title can be more words. And the description should not be empty. Normally those two parts would be commit msg. @benshi001

[barannikov88]

In D153607#4462927, @benshi001 wrote:

In D153607#4462762, @zixuan-wu wrote:

need more case about bhz/bhsz?

It is hard to add tests for

def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),
          (BHZ32 GPR:$rs1, bb:$imm16)>;

Since the original IR pattern

%icmp = icmp sge i32 %x, 1
br i1 %icmp, label %label1, label %label2

is always transformed to an equivalent form by DAGCombiner

%icmp = icmp slt i32 %x, 1
br i1 %icmp, label %label2, label %label1

before reaching to the CSKY backend.

And BHSZ32 has the same issue.

I add these two Pats for BHSZ32 and BHZ32, just in case there is future changes in the DAGCombiner.

Try something like:

extern void on_false(void);
void test_ge_1(int x) {
  if (!(x >= 1))
    on_false();
}

[benshi001]

In D153607#4467587, @barannikov88 wrote:

In D153607#4462927, @benshi001 wrote:

In D153607#4462762, @zixuan-wu wrote:

need more case about bhz/bhsz?

It is hard to add tests for

def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),
          (BHZ32 GPR:$rs1, bb:$imm16)>;

Since the original IR pattern

%icmp = icmp sge i32 %x, 1
br i1 %icmp, label %label1, label %label2

is always transformed to an equivalent form by DAGCombiner

%icmp = icmp slt i32 %x, 1
br i1 %icmp, label %label2, label %label1

before reaching to the CSKY backend.

And BHSZ32 has the same issue.

I add these two Pats for BHSZ32 and BHZ32, just in case there is future changes in the DAGCombiner.

Try something like:

extern void on_false(void);
void test_ge_1(int x) {
  if (!(x >= 1))
    on_false();
}

Unfortunately your program can not lead to BHSZ or BHZ, still BLSZ as follow,

        .type   test_ge_1,@function
test_ge_1:                              # @test_ge_1
# %bb.0:
        subi16  sp, sp, 4
        st32.w  lr, (sp, 0)                     # 4-byte Folded Spill
        blsz32  a0, .LBB0_2
# %bb.1:
        ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
        addi16  sp, sp, 4
        rts16
.LBB0_2:
        jsri32  [.LCPI0_0]
        ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
        addi16  sp, sp, 4
        rts16
        .p2align        1
# %bb.3:
        .p2align        2, 0x0
.LCPI0_0:
        .long   on_false
.Lfunc_end0:
        .size   test_ge_1, .Lfunc_end0-test_ge_1
                                        # -- End function

[benshi001]

This comment was removed by benshi001.

[barannikov88]

In D153607#4467588, @benshi001 wrote:

In D153607#4467587, @barannikov88 wrote:

In D153607#4462927, @benshi001 wrote:

In D153607#4462762, @zixuan-wu wrote:

need more case about bhz/bhsz?

It is hard to add tests for

def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),
          (BHZ32 GPR:$rs1, bb:$imm16)>;

Since the original IR pattern

%icmp = icmp sge i32 %x, 1
br i1 %icmp, label %label1, label %label2

is always transformed to an equivalent form by DAGCombiner

%icmp = icmp slt i32 %x, 1
br i1 %icmp, label %label2, label %label1

before reaching to the CSKY backend.

And BHSZ32 has the same issue.

I add these two Pats for BHSZ32 and BHZ32, just in case there is future changes in the DAGCombiner.

Try something like:

extern void on_false(void);
void test_ge_1(int x) {
  if (!(x >= 1))
    on_false();
}

Unfortunately your program can not lead to BHSZ or BHZ, still BLSZ as follow,

        .type   test_ge_1,@function
test_ge_1:                              # @test_ge_1
# %bb.0:
        subi16  sp, sp, 4
        st32.w  lr, (sp, 0)                     # 4-byte Folded Spill
        blsz32  a0, .LBB0_2
# %bb.1:
        ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
        addi16  sp, sp, 4
        rts16
.LBB0_2:
        jsri32  [.LCPI0_0]
        ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
        addi16  sp, sp, 4
        rts16
        .p2align        1
# %bb.3:
        .p2align        2, 0x0
.LCPI0_0:
        .long   on_false
.Lfunc_end0:
        .size   test_ge_1, .Lfunc_end0-test_ge_1
                                        # -- End function

It does test the pattern though. You can see BHZ32 if you pass -stop-after=finalize-isel.

[benshi001]

In D153607#4467599, @barannikov88 wrote:

In D153607#4467588, @benshi001 wrote:

In D153607#4467587, @barannikov88 wrote:

In D153607#4462927, @benshi001 wrote:

In D153607#4462762, @zixuan-wu wrote:

need more case about bhz/bhsz?

It is hard to add tests for

def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),
          (BHZ32 GPR:$rs1, bb:$imm16)>;

Since the original IR pattern

%icmp = icmp sge i32 %x, 1
br i1 %icmp, label %label1, label %label2

is always transformed to an equivalent form by DAGCombiner

%icmp = icmp slt i32 %x, 1
br i1 %icmp, label %label2, label %label1

before reaching to the CSKY backend.

And BHSZ32 has the same issue.

I add these two Pats for BHSZ32 and BHZ32, just in case there is future changes in the DAGCombiner.

Try something like:

extern void on_false(void);
void test_ge_1(int x) {
  if (!(x >= 1))
    on_false();
}

Unfortunately your program can not lead to BHSZ or BHZ, still BLSZ as follow,

        .type   test_ge_1,@function
test_ge_1:                              # @test_ge_1
# %bb.0:
        subi16  sp, sp, 4
        st32.w  lr, (sp, 0)                     # 4-byte Folded Spill
        blsz32  a0, .LBB0_2
# %bb.1:
        ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
        addi16  sp, sp, 4
        rts16
.LBB0_2:
        jsri32  [.LCPI0_0]
        ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
        addi16  sp, sp, 4
        rts16
        .p2align        1
# %bb.3:
        .p2align        2, 0x0
.LCPI0_0:
        .long   on_false
.Lfunc_end0:
        .size   test_ge_1, .Lfunc_end0-test_ge_1
                                        # -- End function

It does test the pattern though. You can see BHZ32 if you pass -stop-after=finalize-isel.

I still can not get BHZ32/BHSZ32, could you please make another patch for that?

[barannikov88]

I still can not get BHZ32/BHSZ32, could you please make another patch for that?

Sorry, I'm not familiar with architecture. I was just passing by.

llvm/lib/Target/CSKY/CSKYInstrInfo.td

def : Pat<(brcond (i32 (setle GPR:$rs1, GPR:$rs2)), bb:$imm16),
           (BF32 (CMPLT32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
 
 def : Pat<(brcond (i32 (seteq GPR:$rs1, (i32 0))), bb:$imm16),
           (BEZ32 GPR:$rs1, bb:$imm16)>;
 def : Pat<(brcond (i32 (setne GPR:$rs1, (i32 0))), bb:$imm16),
           (BNEZ32 GPR:$rs1, bb:$imm16)>;
 def : Pat<(brcond (i32 (setlt GPR:$rs1, (i32 0))), bb:$imm16),
           (BLZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setlt GPR:$rs1, (i32 1))), bb:$imm16),
+          (BLSZ32 GPR:$rs1, bb:$imm16)>;
 def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 0))), bb:$imm16),
           (BHSZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),
+          (BHZ32 GPR:$rs1, bb:$imm16)>;
 def : Pat<(brcond (i32 (setgt GPR:$rs1, (i32 0))), bb:$imm16),
           (BHZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setgt GPR:$rs1, (i32 -1))), bb:$imm16),
+          (BHSZ32 GPR:$rs1, bb:$imm16)>;
 def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 0))), bb:$imm16),
           (BLSZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 -1))), bb:$imm16),
+          (BLZ32 GPR:$rs1, bb:$imm16)>;
 }
 
 // Compare Patterns.
 let Predicates = [iHas2E3] in {
   def : Pat<(setne GPR:$rs1, GPR:$rs2),
             (CMPNE32 GPR:$rs1, GPR:$rs2)>;
   def : Pat<(i32 (seteq GPR:$rs1, GPR:$rs2)),
             (MVCV32 (CMPNE32 GPR:$rs1, GPR:$rs2))>;

llvm/test/CodeGen/CSKY/br.ll

label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brR0_sgt(i32 %x) {
 ; CHECK-LABEL: brR0_sgt:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmplti16 a0, 1
-; CHECK-NEXT:    bt32 .LBB18_2
+; CHECK-NEXT:    blsz32 a0, .LBB18_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB18_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: brR0_sgt:
label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brR0_slt(i32 %x) {
 ; CHECK-LABEL: brR0_slt:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movih32 a1, 65535
-; CHECK-NEXT:    ori32 a1, a1, 65535
-; CHECK-NEXT:    cmplt16 a1, a0
-; CHECK-NEXT:    bf32 .LBB24_2
+; CHECK-NEXT:    blz32 a0, .LBB24_2
 ; CHECK-NEXT:  # %bb.1: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB24_2: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: brR0_slt:
label1:
   ret i64 1
 label2:
   ret i64 0
 }
 
 define i64 @brR0_i64_slt(i64 %x) {
 ; CHECK-LABEL: brR0_i64_slt:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movih32 a0, 65535
-; CHECK-NEXT:    ori32 a0, a0, 65535
-; CHECK-NEXT:    cmplt16 a0, a1
-; CHECK-NEXT:    bf32 .LBB53_2
+; CHECK-NEXT:    blz32 a1, .LBB53_2
 ; CHECK-NEXT:  # %bb.1: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    movi16 a1, 0
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB53_2: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    movi16 a1, 0
 ; CHECK-NEXT:    rts16

 label2:
   ret i16 0
 }
 
 define i16 @brR0_i16_sgt(i16 %x) {
 ; CHECK-LABEL: brR0_i16_sgt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sexth16 a0, a0
-; CHECK-NEXT:    cmplti16 a0, 1
-; CHECK-NEXT:    bt32 .LBB76_2
+; CHECK-NEXT:    blsz32 a0, .LBB76_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB76_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: brR0_i16_sgt:

 label2:
   ret i16 0
 }
 
 define i16 @brR0_i16_slt(i16 %x) {
 ; CHECK-LABEL: brR0_i16_slt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sexth16 a0, a0
-; CHECK-NEXT:    movih32 a1, 65535
-; CHECK-NEXT:    ori32 a1, a1, 65535
-; CHECK-NEXT:    cmplt16 a1, a0
-; CHECK-NEXT:    bf32 .LBB82_2
+; CHECK-NEXT:    blz32 a0, .LBB82_2
 ; CHECK-NEXT:  # %bb.1: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB82_2: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: brR0_i16_slt:

 label2:
   ret i8 0
 }
 
 define i8 @brR0_i8_sgt(i8 %x) {
 ; CHECK-LABEL: brR0_i8_sgt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sextb16 a0, a0
-; CHECK-NEXT:    cmplti16 a0, 1
-; CHECK-NEXT:    bt32 .LBB105_2
+; CHECK-NEXT:    blsz32 a0, .LBB105_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB105_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: brR0_i8_sgt:

 label2:
   ret i8 0
 }
 
 define i8 @brR0_i8_slt(i8 %x) {
 ; CHECK-LABEL: brR0_i8_slt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sextb16 a0, a0
-; CHECK-NEXT:    movih32 a1, 65535
-; CHECK-NEXT:    ori32 a1, a1, 65535
-; CHECK-NEXT:    cmplt16 a1, a0
-; CHECK-NEXT:    bf32 .LBB111_2
+; CHECK-NEXT:    blz32 a0, .LBB111_2
 ; CHECK-NEXT:  # %bb.1: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB111_2: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: brR0_i8_slt: