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Differential D15322

Define selection for v4f16, v8f16 scalar_to_vector
ClosedPublic

Authored by pirama on Dec 7 2015, 8:00 PM.

Details

Reviewers
ab
jmolloy
Commits
rGe6ccd7b66a55: Define selection for v4f16, v8f16 scalar_to_vector
rL255072: Define selection for v4f16, v8f16 scalar_to_vector
Summary

This fixes failure when trying to select

insertelement <4 x half> undef, half %a, i64 0

which gets transformed to a scalar_to_vector node.

The accompanying v4 and v8 tests fail instruction selection without this
patch.

Diff Detail

Event Timeline

pirama updated this revision to Diff 42135.Dec 7 2015, 8:00 PM
pirama retitled this revision from to Define selection for v4f16, v8f16 scalar_to_vector.
pirama updated this object.
pirama added reviewers: ab, jmolloy.
pirama added subscribers: llvm-commits, srhines.
jmolloy accepted this revision.Dec 8 2015, 1:50 AM
jmolloy edited edge metadata.

This LGTM.

This revision is now accepted and ready to land.Dec 8 2015, 1:50 AM
Closed by commit rL255072: Define selection for v4f16, v8f16 scalar_to_vector (authored by pirama). · Explain WhyDec 8 2015, 3:10 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AArch64/
5 lines
test/
CodeGen/
AArch64/
9 lines
9 lines

Diff 42135

lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,805 Lines • ▼ Show 20 Linesdef : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
(i32 FPR32:$Rn), ssub))>; (i32 FPR32:$Rn), ssub))>;
def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))), def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
(i32 FPR32:$Rn), ssub))>; (i32 FPR32:$Rn), ssub))>;
def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))), def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
(v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
(i64 FPR64:$Rn), dsub))>; (i64 FPR64:$Rn), dsub))>;
def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))),
(INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))), def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))), def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))), def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>; (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn), def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
▲ Show 20 Lines • Show All 2,131 Lines • Show Last 20 Lines

test/CodeGen/AArch64/fp16-v4-instructions.ll

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Lines
; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]] ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
%1 = uitofp <4 x i64> %a to <4 x half> %1 = uitofp <4 x i64> %a to <4 x half>
ret <4 x half> %1 ret <4 x half> %1
} }
define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 {
; CHECK-LABEL: test_insert_at_zero:
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%1 = insertelement <4 x half> undef, half %a, i64 0
store <4 x half> %1, <4 x half>* %b, align 4
ret void
}
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AArch64/fp16-v8-instructions.ll

Show First 20 Lines • Show All 352 Lines • ▼ Show 20 Lines
; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]] ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
; CHECK: fcvtn v0.4h, [[OP3]].4s ; CHECK: fcvtn v0.4h, [[OP3]].4s
%1 = uitofp <8 x i64> %a to <8 x half> %1 = uitofp <8 x i64> %a to <8 x half>
ret <8 x half> %1 ret <8 x half> %1
} }
define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 {
; CHECK-LABEL: test_insert_at_zero:
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%1 = insertelement <8 x half> undef, half %a, i64 0
store <8 x half> %1, <8 x half>* %b, align 4
ret void
}
attributes #0 = { nounwind } attributes #0 = { nounwind }