[LoongArch] Fix handling of the chain of CSRWR and CSRXCHG nodes

[SixWeining]

Summary

LoongArchISD::CSRWR has two results. The first is the result of
loongarch.csrwr.[wd] intrinsic and the second is the chain. But
currently the chain is not processed correctly when creating this
node, resulting in the csrwr instruction being optimized out when
the result is not used by anyone [1]. LoongArchISD::CSRXCHG has
the same issue.

This patch addresses this issue.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.4-rc6#n219

[hev]

Thanks.

[SixWeining]

rebase and update commit message (add a link to linux source code)

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

enum NodeType : unsigned {
   CRC_W_W_W,
   CRC_W_D_W,
   CRCC_W_B_W,
   CRCC_W_H_W,
   CRCC_W_W_W,
   CRCC_W_D_W,
 
   CSRRD,
+
+  // Write new value to CSR and return old value.
+  // Operand 0: A chain pointer.
+  // Operand 1: The new value to write.
+  // Operand 2: The address of the required CSR.
+  // Result 0: The old value of the CSR.
+  // Result 1: The new chain pointer.
   CSRWR,
+
+  // Similar to CSRWR but with a write mask.
+  // Operand 0: A chain pointer.
+  // Operand 1: The new value to write.
+  // Operand 2: The write mask.
+  // Operand 3: The address of the required CSR.
+  // Result 0: The old value of the CSR.
+  // Result 1: The new chain pointer.
   CSRXCHG,
 
   // IOCSR access operations
   IOCSRRD_B,
   IOCSRRD_W,
   IOCSRRD_H,
   IOCSRRD_D,
   IOCSRWR_B,

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

return !isUInt<14>(Imm)
                       Chain},
                      DL);
   }
   case Intrinsic::loongarch_csrwr_w:
   case Intrinsic::loongarch_csrwr_d: {
     unsigned Imm = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
     return !isUInt<14>(Imm)
                ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
-               : DAG.getMergeValues(
-                     {DAG.getNode(LoongArchISD::CSRWR, DL, GRLenVT, Chain,
-                                  Op.getOperand(2),
-                                  DAG.getConstant(Imm, DL, GRLenVT)),
-                      Chain},
-                     DL);
+               : DAG.getNode(LoongArchISD::CSRWR, DL, {GRLenVT, MVT::Other},
+                             {Chain, Op.getOperand(2),
+                              DAG.getConstant(Imm, DL, GRLenVT)});
   }
   case Intrinsic::loongarch_csrxchg_w:
   case Intrinsic::loongarch_csrxchg_d: {
     unsigned Imm = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
     return !isUInt<14>(Imm)
                ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
-               : DAG.getMergeValues(
-                     {DAG.getNode(LoongArchISD::CSRXCHG, DL, GRLenVT, Chain,
-                                  Op.getOperand(2), Op.getOperand(3),
-                                  DAG.getConstant(Imm, DL, GRLenVT)),
-                      Chain},
-                     DL);
+               : DAG.getNode(LoongArchISD::CSRXCHG, DL, {GRLenVT, MVT::Other},
+                             {Chain, Op.getOperand(2), Op.getOperand(3),
+                              DAG.getConstant(Imm, DL, GRLenVT)});
   }
   case Intrinsic::loongarch_iocsrrd_d: {
     return DAG.getMergeValues(
         {DAG.getNode(
              LoongArchISD::IOCSRRD_D, DL, GRLenVT, Chain,
              DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2))),
          Chain},
         DL);
#undef CSR_CASE
     }
     case Intrinsic::loongarch_csrwr_w: {
       unsigned Imm = cast<ConstantSDNode>(N->getOperand(3))->getZExtValue();
       if (!isUInt<14>(Imm)) {
         emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
                                                      ErrorMsgOOR);
         return;
       }
-      Results.push_back(DAG.getNode(
-          ISD::TRUNCATE, DL, VT,
-          DAG.getNode(LoongArchISD::CSRWR, DL, GRLenVT, Chain,
-                      DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
-                      DAG.getConstant(Imm, DL, GRLenVT))));
-      Results.push_back(Chain);
+      SDValue CSRWRResults =
+          DAG.getNode(LoongArchISD::CSRWR, DL, {GRLenVT, MVT::Other},
+                      {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
+                       DAG.getConstant(Imm, DL, GRLenVT)});
+      Results.push_back(
+          DAG.getNode(ISD::TRUNCATE, DL, VT, CSRWRResults.getValue(0)));
+      Results.push_back(CSRWRResults.getValue(1));
       break;
     }
     case Intrinsic::loongarch_csrxchg_w: {
       unsigned Imm = cast<ConstantSDNode>(N->getOperand(4))->getZExtValue();
       if (!isUInt<14>(Imm)) {
         emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
                                                      ErrorMsgOOR);
         return;
       }
-      Results.push_back(DAG.getNode(
-          ISD::TRUNCATE, DL, VT,
-          DAG.getNode(
-              LoongArchISD::CSRXCHG, DL, GRLenVT, Chain,
-              DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
-              DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3)),
-              DAG.getConstant(Imm, DL, GRLenVT))));
-      Results.push_back(Chain);
+      SDValue CSRXCHGResults = DAG.getNode(
+          LoongArchISD::CSRXCHG, DL, {GRLenVT, MVT::Other},
+          {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
+           DAG.getConstant(Imm, DL, GRLenVT)});
+      Results.push_back(
+          DAG.getNode(ISD::TRUNCATE, DL, VT, CSRXCHGResults.getValue(0)));
+      Results.push_back(CSRXCHGResults.getValue(1));
       break;
     }
 #define IOCSRRD_CASE(NAME, NODE)                                               \
   case Intrinsic::loongarch_##NAME: {                                          \
     Results.push_back(DAG.getNode(                                             \
         ISD::TRUNCATE, DL, VT,                                                 \
         DAG.getNode(LoongArchISD::NODE, DL, MVT::i64, Chain,                   \
                     DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2))));        \

llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

 ; CHECK-NEXT:    csrwr $a0, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
   ret i64 %0
 }
 
 ;; Check that csrwr is emitted even if the return value of the intrinsic is not used.
-;; FIXME: currently csrwr is not emitted.
 define void @csrwr_d_noret(i64 %a) {
 ; CHECK-LABEL: csrwr_d_noret:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrwr $a0, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
   ret void
 }
 
 define i64 @csrxchg_d(i64 %a, i64 %b) {
 ; CHECK-LABEL: csrxchg_d:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    csrxchg $a0, $a1, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
   ret i64 %0
 }
 
 ;; Check that csrxchg is emitted even if the return value of the intrinsic is not used.
-;; FIXME: currently csrxchg is not emitted.
 define void @csrxchg_d_noret(i64 %a, i64 %b) {
 ; CHECK-LABEL: csrxchg_d_noret:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrxchg $a0, $a1, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
   ret void
 }
 
 define i64 @iocsrrd_d(i32 %a) {
 ; CHECK-LABEL: iocsrrd_d:

llvm/test/CodeGen/LoongArch/intrinsic.ll

 ; CHECK-NEXT:    csrwr $a0, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
   ret i32 %0
 }
 
 ;; Check that csrwr is emitted even if the return value of the intrinsic is not used.
-;; FIXME: currently csrwr is not emitted.
 define void @csrwr_w_noret(i32 signext %a) {
 ; CHECK-LABEL: csrwr_w_noret:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrwr $a0, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
   ret void
 }
 
 define i32 @csrxchg_w(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: csrxchg_w:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    csrxchg $a0, $a1, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
   ret i32 %0
 }
 
 ;; Check that csrxchg is emitted even if the return value of the intrinsic is not used.
-;; FIXME: currently csrxchg is not emitted.
 define void @csrxchg_w_noret(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: csrxchg_w_noret:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrxchg $a0, $a1, 1
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
   ret void
 }
 
 define i32 @iocsrrd_b(i32 %a) {
 ; CHECK-LABEL: iocsrrd_b: