This is an archive of the discontinued LLVM Phabricator instance.

Differential D153119

[LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG)
ClosedPublic

Authored by SixWeining on Jun 16 2023, 3:02 AM.

Details

Reviewers
hev
xen0n
xry111
wangleiat
Commits
rG4a69fd62699e: [LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG)

Diff Detail

Event Timeline

SixWeining created this revision.Jun 16 2023, 3:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 16 2023, 3:02 AM
SixWeining requested review of this revision.Jun 16 2023, 3:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 16 2023, 3:02 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
SixWeining added a child revision: D153120: [LoongArch] Fix handling of the chain of CSRWR and CSRXCHG nodes.Jun 16 2023, 3:03 AM
Harbormaster completed remote builds in B239361: Diff 532067.Jun 16 2023, 3:55 AM
xry111 accepted this revision.Jun 16 2023, 8:28 AM
xry111 retitled this revision from [LoongArch] Precommit test for the fix of CSRWR and CSRXCHG to [LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG).

LGTM.

This revision is now accepted and ready to land.Jun 16 2023, 8:29 AM
hev accepted this revision.Jun 16 2023, 7:26 PM
SixWeining updated this revision to Diff 532353.Jun 16 2023, 7:51 PM

rebase

This revision was landed with ongoing or failed builds.Jun 16 2023, 7:56 PM
Closed by commit rG4a69fd62699e: [LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG) (authored by SixWeining). · Explain Why
This revision was automatically updated to reflect the committed changes.
SixWeining added a commit: rG4a69fd62699e: [LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG).
Harbormaster completed remote builds in B239573: Diff 532353.Jun 16 2023, 8:26 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
LoongArch/
22 lines
22 lines

Diff 532355

llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrwr $a0, 1 ; CHECK-NEXT: csrwr $a0, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1) %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
ret i64 %0 ret i64 %0
} }
;; Check that csrwr is emitted even if the return value of the intrinsic is not used.
;; FIXME: currently csrwr is not emitted.
define void @csrwr_d_noret(i64 %a) {
; CHECK-LABEL: csrwr_d_noret:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
ret void
}
define i64 @csrxchg_d(i64 %a, i64 %b) { define i64 @csrxchg_d(i64 %a, i64 %b) {
; CHECK-LABEL: csrxchg_d: ; CHECK-LABEL: csrxchg_d:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrxchg $a0, $a1, 1 ; CHECK-NEXT: csrxchg $a0, $a1, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1) %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
ret i64 %0 ret i64 %0
} }
;; Check that csrxchg is emitted even if the return value of the intrinsic is not used.
;; FIXME: currently csrxchg is not emitted.
define void @csrxchg_d_noret(i64 %a, i64 %b) {
; CHECK-LABEL: csrxchg_d_noret:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
ret void
}
define i64 @iocsrrd_d(i32 %a) { define i64 @iocsrrd_d(i32 %a) {
; CHECK-LABEL: iocsrrd_d: ; CHECK-LABEL: iocsrrd_d:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: iocsrrd.d $a0, $a0 ; CHECK-NEXT: iocsrrd.d $a0, $a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.loongarch.iocsrrd.d(i32 %a) %0 = tail call i64 @llvm.loongarch.iocsrrd.d(i32 %a)
ret i64 %0 ret i64 %0
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/LoongArch/intrinsic.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrwr $a0, 1 ; CHECK-NEXT: csrwr $a0, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1) %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
ret i32 %0 ret i32 %0
} }
;; Check that csrwr is emitted even if the return value of the intrinsic is not used.
;; FIXME: currently csrwr is not emitted.
define void @csrwr_w_noret(i32 signext %a) {
; CHECK-LABEL: csrwr_w_noret:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
ret void
}
define i32 @csrxchg_w(i32 signext %a, i32 signext %b) { define i32 @csrxchg_w(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: csrxchg_w: ; CHECK-LABEL: csrxchg_w:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrxchg $a0, $a1, 1 ; CHECK-NEXT: csrxchg $a0, $a1, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1) %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
ret i32 %0 ret i32 %0
} }
;; Check that csrxchg is emitted even if the return value of the intrinsic is not used.
;; FIXME: currently csrxchg is not emitted.
define void @csrxchg_w_noret(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: csrxchg_w_noret:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
ret void
}
define i32 @iocsrrd_b(i32 %a) { define i32 @iocsrrd_b(i32 %a) {
; CHECK-LABEL: iocsrrd_b: ; CHECK-LABEL: iocsrrd_b:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: iocsrrd.b $a0, $a0 ; CHECK-NEXT: iocsrrd.b $a0, $a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i32 @llvm.loongarch.iocsrrd.b(i32 %a) %0 = tail call i32 @llvm.loongarch.iocsrrd.b(i32 %a)
ret i32 %0 ret i32 %0
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines