[CSKY][NFC][test] Add more tests of multiplication with immediates

[benshi001]

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

119 ↗

(On Diff #532576)

This is modified by clang-format.

llvm/lib/Target/CSKY/CSKY.td

 def FeatureFdivdu : SubtargetFeature<"fdivdu", "HasFdivdu", "true",
                                      "Enable float divide instructions">;
 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
                 AssemblerPredicate<(all_of FeatureFdivdu),
                 "Enable float divide instructions">;
 
 def FeatureFPUV3_HI
     : SubtargetFeature<"fpuv3_hi", "HasFPUv3HalfWord", "true",
-                       "Enable FPUv3 harf word converting instructions">;
+                       "Enable FPUv3 half word converting instructions">;
 def HasFPUv3_HI : Predicate<"Subtarget->hasFPUv3HalfWord()">,
                   AssemblerPredicate<(all_of FeatureFPUV3_HI),
-                  "Enable FPUv3 harf word converting instructions">;
+                  "Enable FPUv3 half word converting instructions">;
 
 def FeatureFPUV3_HF
     : SubtargetFeature<"fpuv3_hf", "HasFPUv3HalfFloat", "true",
-                       "Enable FPUv3 harf precision operate instructions">;
+                       "Enable FPUv3 half precision operate instructions">;
 def HasFPUv3_HF : Predicate<"Subtarget->hasFPUv3HalfFloat()">,
                   AssemblerPredicate<(all_of FeatureFPUV3_HF),
-                  "Enable FPUv3 harf precision operate instructions">;
+                  "Enable FPUv3 half precision operate instructions">;
 
 def FeatureFPUV3_SF
     : SubtargetFeature<"fpuv3_sf", "HasFPUv3SingleFloat", "true",
                        "Enable FPUv3 single float instructions">;
 def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">,
                   AssemblerPredicate<(all_of FeatureFPUV3_SF),
                   "Enable FPUv3 single float instructions">;
 

llvm/test/CodeGen/CSKY/base-i.ll

 ; GENERIC-NEXT:    mult16 a0, a1
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %mul = mul nsw i32 %x, 4097
   ret i32 %mul
 }
 
+define i32 @mulRI_4095(i32 %x) {
+; CHECK-LABEL: mulRI_4095:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movi32 a1, 4095
+; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    rts16
+;
+; GENERIC-LABEL: mulRI_4095:
+; GENERIC:       # %bb.0: # %entry
+; GENERIC-NEXT:    .cfi_def_cfa_offset 0
+; GENERIC-NEXT:    subi16 sp, sp, 4
+; GENERIC-NEXT:    .cfi_def_cfa_offset 4
+; GENERIC-NEXT:    movi16 a1, 0
+; GENERIC-NEXT:    lsli16 a2, a1, 24
+; GENERIC-NEXT:    lsli16 a1, a1, 16
+; GENERIC-NEXT:    or16 a1, a2
+; GENERIC-NEXT:    movi16 a2, 15
+; GENERIC-NEXT:    lsli16 a2, a2, 8
+; GENERIC-NEXT:    or16 a2, a1
+; GENERIC-NEXT:    movi16 a1, 255
+; GENERIC-NEXT:    or16 a1, a2
+; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    addi16 sp, sp, 4
+; GENERIC-NEXT:    rts16
+entry:
+  %mul = mul nsw i32 %x, 4095
+  ret i32 %mul
+}
+
+define i32 @mulRI_minus_4095(i32 %x) {
+; CHECK-LABEL: mulRI_minus_4095:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movih32 a1, 65535
+; CHECK-NEXT:    ori32 a1, a1, 61441
+; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    rts16
+;
+; GENERIC-LABEL: mulRI_minus_4095:
+; GENERIC:       # %bb.0: # %entry
+; GENERIC-NEXT:    .cfi_def_cfa_offset 0
+; GENERIC-NEXT:    subi16 sp, sp, 4
+; GENERIC-NEXT:    .cfi_def_cfa_offset 4
+; GENERIC-NEXT:    movi16 a1, 255
+; GENERIC-NEXT:    lsli16 a2, a1, 24
+; GENERIC-NEXT:    lsli16 a1, a1, 16
+; GENERIC-NEXT:    or16 a1, a2
+; GENERIC-NEXT:    movi16 a2, 240
+; GENERIC-NEXT:    lsli16 a2, a2, 8
+; GENERIC-NEXT:    or16 a2, a1
+; GENERIC-NEXT:    movi16 a1, 1
+; GENERIC-NEXT:    or16 a1, a2
+; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    addi16 sp, sp, 4
+; GENERIC-NEXT:    rts16
+entry:
+  %mul = mul nsw i32 %x, -4095
+  ret i32 %mul
+}
+
+define i32 @mulRI_minus_4097(i32 %x) {
+; CHECK-LABEL: mulRI_minus_4097:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movih32 a1, 65535
+; CHECK-NEXT:    ori32 a1, a1, 61439
+; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    rts16
+;
+; GENERIC-LABEL: mulRI_minus_4097:
+; GENERIC:       # %bb.0: # %entry
+; GENERIC-NEXT:    .cfi_def_cfa_offset 0
+; GENERIC-NEXT:    subi16 sp, sp, 4
+; GENERIC-NEXT:    .cfi_def_cfa_offset 4
+; GENERIC-NEXT:    movi16 a1, 255
+; GENERIC-NEXT:    lsli16 a2, a1, 24
+; GENERIC-NEXT:    lsli16 a3, a1, 16
+; GENERIC-NEXT:    or16 a3, a2
+; GENERIC-NEXT:    movi16 a2, 239
+; GENERIC-NEXT:    lsli16 a2, a2, 8
+; GENERIC-NEXT:    or16 a2, a3
+; GENERIC-NEXT:    or16 a2, a1
+; GENERIC-NEXT:    mult16 a0, a2
+; GENERIC-NEXT:    addi16 sp, sp, 4
+; GENERIC-NEXT:    rts16
+entry:
+  %mul = mul nsw i32 %x, -4097
+  ret i32 %mul
+}
+
 define i16 @MUL_SHORT(i16 %x, i16 %y) {
 ; CHECK-LABEL: MUL_SHORT:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mult16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: MUL_SHORT:
 ; GENERIC:       # %bb.0: # %entry

 ; GENERIC-NEXT:    mult16 a0, a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %mul = mul nsw i8 %x, -3
   ret i8 %mul
 }
 
+define i64 @MUL_LONG_I(i64 %x) {
+; CHECK-LABEL: MUL_LONG_I:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subi16 sp, sp, 4
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset lr, -4
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    movi32 a2, 4095
+; CHECK-NEXT:    movi16 a3, 0
+; CHECK-NEXT:    jsri32 [.LCPI28_0]
+; CHECK-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT:    addi16 sp, sp, 4
+; CHECK-NEXT:    rts16
+; CHECK-NEXT:    .p2align 1
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    .p2align 2, 0x0
+; CHECK-NEXT:  .LCPI28_0:
+; CHECK-NEXT:    .long __muldi3
+;
+; GENERIC-LABEL: MUL_LONG_I:
+; GENERIC:       # %bb.0: # %entry
+; GENERIC-NEXT:    subi16 sp, sp, 8
+; GENERIC-NEXT:    .cfi_def_cfa_offset 8
+; GENERIC-NEXT:    st16.w l0, (sp, 4) # 4-byte Folded Spill
+; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
+; GENERIC-NEXT:    .cfi_offset l0, -4
+; GENERIC-NEXT:    .cfi_offset lr, -8
+; GENERIC-NEXT:    subi16 sp, sp, 4
+; GENERIC-NEXT:    .cfi_def_cfa_offset 12
+; GENERIC-NEXT:    movi16 a2, 0
+; GENERIC-NEXT:    lsli16 a3, a2, 24
+; GENERIC-NEXT:    lsli16 a2, a2, 16
+; GENERIC-NEXT:    or16 a2, a3
+; GENERIC-NEXT:    movi16 a3, 15
+; GENERIC-NEXT:    lsli16 a3, a3, 8
+; GENERIC-NEXT:    or16 a3, a2
+; GENERIC-NEXT:    movi16 a2, 255
+; GENERIC-NEXT:    or16 a2, a3
+; GENERIC-NEXT:    lrw32 l0, [.LCPI28_0]
+; GENERIC-NEXT:    movi16 a3, 0
+; GENERIC-NEXT:    jsr16 l0
+; GENERIC-NEXT:    addi16 sp, sp, 4
+; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; GENERIC-NEXT:    ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; GENERIC-NEXT:    addi16 sp, sp, 8
+; GENERIC-NEXT:    rts16
+; GENERIC-NEXT:    .p2align 1
+; GENERIC-NEXT:  # %bb.1:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI28_0:
+; GENERIC-NEXT:    .long __muldi3
+entry:
+  %mul = mul nsw i64 %x, 4095
+  ret i64 %mul
+}
+
 define i32 @udivRR(i32 %x, i32 %y) {
 ; CHECK-LABEL: udivRR:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    divu32 a0, a1, a0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: udivRR:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; GENERIC-NEXT:    .cfi_offset lr, -4
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    mov16 a2, a0
-; GENERIC-NEXT:    lrw32 a3, [.LCPI25_0]
+; GENERIC-NEXT:    lrw32 a3, [.LCPI29_0]
 ; GENERIC-NEXT:    mov16 a0, a1
 ; GENERIC-NEXT:    mov16 a1, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI25_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI29_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i32 %y, %x
   ret i32 %udiv
 }
 
 define i32 @udivRI(i32 %x) {
 ; CHECK-LABEL: udivRI:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movi16 a1, 10
 ; CHECK-NEXT:    divu32 a0, a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: udivRI:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; GENERIC-NEXT:    .cfi_offset lr, -4
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
-; GENERIC-NEXT:    lrw32 a2, [.LCPI26_0]
+; GENERIC-NEXT:    lrw32 a2, [.LCPI30_0]
 ; GENERIC-NEXT:    movi16 a1, 10
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI26_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI30_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i32 %x, 10
   ret i32 %udiv
 }
 
 define i32 @udivRI_X(i32 %x) {
 ; CHECK-LABEL: udivRI_X:

 ; GENERIC-NEXT:    lsli16 a2, a1, 24
 ; GENERIC-NEXT:    lsli16 a1, a1, 16
 ; GENERIC-NEXT:    or16 a1, a2
 ; GENERIC-NEXT:    movi16 a2, 16
 ; GENERIC-NEXT:    lsli16 a2, a2, 8
 ; GENERIC-NEXT:    or16 a2, a1
 ; GENERIC-NEXT:    movi16 a1, 1
 ; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    lrw32 a2, [.LCPI27_0]
+; GENERIC-NEXT:    lrw32 a2, [.LCPI31_0]
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI27_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI31_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i32 %x, 4097
   ret i32 %udiv
 }
 
 define i16 @UDIV_SHORT(i16 %x, i16 %y) {
 ; CHECK-LABEL: UDIV_SHORT:

 ; GENERIC-NEXT:    lsli16 l0, a1, 16
 ; GENERIC-NEXT:    or16 l0, a3
 ; GENERIC-NEXT:    movi16 a3, 255
 ; GENERIC-NEXT:    lsli16 a1, a3, 8
 ; GENERIC-NEXT:    or16 a1, l0
 ; GENERIC-NEXT:    or16 a1, a3
 ; GENERIC-NEXT:    and16 a2, a1
 ; GENERIC-NEXT:    and16 a1, a0
-; GENERIC-NEXT:    lrw32 a3, [.LCPI28_0]
+; GENERIC-NEXT:    lrw32 a3, [.LCPI32_0]
 ; GENERIC-NEXT:    mov16 a0, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    ld16.w l0, (sp, 4) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 8
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI28_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI32_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i16 %y, %x
   ret i16 %udiv
 }
 
 define i16 @UDIV_SHORT_I(i16 %x) {
 ; CHECK-LABEL: UDIV_SHORT_I:

 ; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; GENERIC-NEXT:    .cfi_offset lr, -4
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    mov16 a2, a1
 ; GENERIC-NEXT:    movi16 a1, 255
 ; GENERIC-NEXT:    and16 a2, a1
 ; GENERIC-NEXT:    and16 a1, a0
-; GENERIC-NEXT:    lrw32 a3, [.LCPI30_0]
+; GENERIC-NEXT:    lrw32 a3, [.LCPI34_0]
 ; GENERIC-NEXT:    mov16 a0, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI30_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI34_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i8 %y, %x
   ret i8 %udiv
 }
 
 define i8 @UDIV_CHAR_I(i8 %x) {
 ; CHECK-LABEL: UDIV_CHAR_I:

 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; GENERIC-NEXT:    .cfi_offset lr, -4
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    mov16 a2, a0
-; GENERIC-NEXT:    lrw32 a3, [.LCPI32_0]
+; GENERIC-NEXT:    lrw32 a3, [.LCPI36_0]
 ; GENERIC-NEXT:    mov16 a0, a1
 ; GENERIC-NEXT:    mov16 a1, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI32_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI36_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i32 %y, %x
   ret i32 %sdiv
 }
 
 define i32 @sdivRI(i32 %x) {
 ; CHECK-LABEL: sdivRI:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movi16 a1, 10
 ; CHECK-NEXT:    divs32 a0, a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: sdivRI:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; GENERIC-NEXT:    .cfi_offset lr, -4
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
-; GENERIC-NEXT:    lrw32 a2, [.LCPI33_0]
+; GENERIC-NEXT:    lrw32 a2, [.LCPI37_0]
 ; GENERIC-NEXT:    movi16 a1, 10
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI33_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI37_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i32 %x, 10
   ret i32 %sdiv
 }
 
 define i32 @sdivRI_X(i32 %x) {
 ; CHECK-LABEL: sdivRI_X:

 ; GENERIC-NEXT:    lsli16 a2, a1, 24
 ; GENERIC-NEXT:    lsli16 a1, a1, 16
 ; GENERIC-NEXT:    or16 a1, a2
 ; GENERIC-NEXT:    movi16 a2, 16
 ; GENERIC-NEXT:    lsli16 a2, a2, 8
 ; GENERIC-NEXT:    or16 a2, a1
 ; GENERIC-NEXT:    movi16 a1, 1
 ; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    lrw32 a2, [.LCPI34_0]
+; GENERIC-NEXT:    lrw32 a2, [.LCPI38_0]
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI34_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI38_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i32 %x, 4097
   ret i32 %sdiv
 }
 
 define i16 @SDIV_SHORT(i16 %x, i16 %y) {
 ; CHECK-LABEL: SDIV_SHORT:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sexth16 a0, a0
 ; CHECK-NEXT:    sexth16 a1, a1
 ; CHECK-NEXT:    divs32 a0, a1, a0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: SDIV_SHORT:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; GENERIC-NEXT:    .cfi_offset lr, -4
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    sexth16 a2, a1
 ; GENERIC-NEXT:    sexth16 a1, a0
-; GENERIC-NEXT:    lrw32 a3, [.LCPI35_0]
+; GENERIC-NEXT:    lrw32 a3, [.LCPI39_0]
 ; GENERIC-NEXT:    mov16 a0, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI35_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI39_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i16 %y, %x
   ret i16 %sdiv
 }
 
 define i16 @SDIV_SHORT_I(i16 %x) {
 ; CHECK-LABEL: SDIV_SHORT_I:

 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; GENERIC-NEXT:    .cfi_offset lr, -4
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    sextb16 a2, a1
 ; GENERIC-NEXT:    sextb16 a1, a0
-; GENERIC-NEXT:    lrw32 a3, [.LCPI37_0]
+; GENERIC-NEXT:    lrw32 a3, [.LCPI41_0]
 ; GENERIC-NEXT:    mov16 a0, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
-; GENERIC-NEXT:  .LCPI37_0:
+; GENERIC-NEXT:    .p2align 2, 0x0
+; GENERIC-NEXT:  .LCPI41_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i8 %y, %x
   ret i8 %sdiv
 }
 
 define i8 @SDIV_CHAR_I(i8 %x) {
 ; CHECK-LABEL: SDIV_CHAR_I: