[CSKY] Optimize multiplication with immediates

[benshi001]

Summary

Try to break a multiplication with a specific immediate to
an/a addition/subtraction of left shifts.

[zixuan-wu]

It's better to add extra test case file to test every condition of // Break MULT into LSLI + ADDU/SUBU.

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

119–121

No related code change.

1386

As this line code shows, it try to avoid data type larger than machine register size. And, CSKY is always 32-bit machine.

1394

Does (-1 - Imm).isPowerOf2() also make sense?

[benshi001]

Thanks. I will create a new test file for all the cases.

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

119–121

This is modified by clang-format.

1394

(-1 - Imm).isPowerOf2() will generate more instructions, I am not sure this is a win, though the multiplication is eliminated. So I left (-1 - Imm) unchanged. Maybe we can decide this case later.

[benshi001]

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

1394

Especially, for example,

a * -4097 will be generated to

lsli16, a1, a0, 12
addu16 a1, a0
movi16 a0, 0
subu16 a0, a1

An extra 'movi16` is needed.

[benshi001]

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

1386

Thanks. I have fixed this issue in my new uploaded patch.

[benshi001]

llvm/test/CodeGen/CSKY/mul-imm.ll

270

This is the negative case, which can not be optimized due to data size exceeds 32-bit.

[zixuan-wu]

LGTM. With minor change that the title of this revision can be more concrete.

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

1386

Can the 32 hard code be const variable which can be defined in Subtarget consistently?

[benshi001]

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

1386

Done. I have created a CSKYSubtarget::getDataSizeInBits() for that.

[benshi001]

This patch relies on https://reviews.llvm.org/D153105, which also needs your approval.

[zixuan-wu]

llvm/lib/Target/CSKY/CSKYSubtarget.h

210

I think the name getDataSizeInBits is not precise about target machine.

static const unsigned XLEN = 32;

may be better?

[benshi001]

llvm/lib/Target/CSKY/CSKYSubtarget.h

210

I prefer const unsigned XLen = 32;.

[zixuan-wu]

llvm/lib/Target/CSKY/CSKYSubtarget.h

210

LGTM

llvm/lib/Target/CSKY/CSKYISelLowering.h

private:
   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
                            bool UseGOT) const;
   SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
 
   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
   CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg) const;
+
+  bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
+                              SDValue C) const override;
 };
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_CSKY_CSKYISELLOWERING_H

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
 
   // Float
 
   ISD::CondCode FPCCToExtend[] = {
       ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
       ISD::SETUGE, ISD::SETULT, ISD::SETULE,
   };
 
   ISD::NodeType FPOpToExpand[] = {
       ISD::FSIN, ISD::FCOS,      ISD::FSINCOS,    ISD::FPOW,
       ISD::FREM, ISD::FCOPYSIGN, ISD::FP16_TO_FP, ISD::FP_TO_FP16};
 
   if (STI.useHardFloat()) {
 
     MVT AllVTy[] = {MVT::f32, MVT::f64};
 
     for (auto VT : AllVTy) {
       setOperationAction(ISD::FREM, VT, Expand);
       setOperationAction(ISD::SELECT_CC, VT, Expand);
CLI.setDebugLoc(DL)
       .setChain(DAG.getEntryNode())
       .setLibCallee(CallingConv::C, CallTy,
                     DAG.getExternalSymbol("__tls_get_addr", Ty),
                     std::move(Args));
   SDValue V = LowerCallTo(CLI).first;
 
   return V;
 }
+
+bool CSKYTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
+                                                SDValue C) const {
+  if (!VT.isScalarInteger())
+    return false;
+
+  // Omit if data size exceeds.
+  if (VT.getSizeInBits() > Subtarget.XLen)
+    return false;
+
+  if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
+    const APInt &Imm = ConstNode->getAPIntValue();
+    // Break MULT to LSLI + ADDU/SUBU.
+    if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
+        (1 - Imm).isPowerOf2())
+      return true;
+    // Only break MULT for sub targets without MULT32, since an extra
+    // instruction will be generated against the above 3 cases. We leave it
+    // unchanged on sub targets with MULT32, since not sure it is better.
+    if (!Subtarget.hasE2() && (-1 - Imm).isPowerOf2())
+      return true;
+  }
+
+  return false;
+}

llvm/lib/Target/CSKY/CSKYSubtarget.h

public:
   bool isCK803S() const { return CSKYProcFamily == CK803S; }
   bool isCK804() const { return CSKYProcFamily == CK804; }
   bool isCK805() const { return CSKYProcFamily == CK805; }
   bool isCK807() const { return CSKYProcFamily == CK807; }
   bool isCK810() const { return CSKYProcFamily == CK810; }
   bool isCK810V() const { return CSKYProcFamily == CK810V; }
   bool isCK860() const { return CSKYProcFamily == CK860; }
   bool isCK860V() const { return CSKYProcFamily == CK860V; }
+
+  const unsigned XLen = 32;
 };
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_CSKY_CSKYSUBTARGET_H

llvm/test/CodeGen/CSKY/base-i.ll

 entry:
   %mul = mul nsw i32 %x, 10
   ret i32 %mul
 }
 
 define i32 @mulRI_X(i32 %x) {
 ; CHECK-LABEL: mulRI_X:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi32 a1, 4097
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 12
+; CHECK-NEXT:    addu16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mulRI_X:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 0
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a1, a1, 16
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    movi16 a2, 16
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    movi16 a1, 1
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    addu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %mul = mul nsw i32 %x, 4097
   ret i32 %mul
 }
 
 define i16 @MUL_SHORT(i16 %x, i16 %y) {

 entry:
   %mul = mul nsw i16 %y, %x
   ret i16 %mul
 }
 
 define i16 @MUL_SHORT_I(i16 %x) {
 ; CHECK-LABEL: MUL_SHORT_I:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi16 a1, 3
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    ixh32 a0, a0, a0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: MUL_SHORT_I:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 3
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 1
+; GENERIC-NEXT:    addu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %mul = mul nsw i16 %x, 3
   ret i16 %mul
 }
 
 define i8 @MUL_CHAR(i8 %x, i8 %y) {

 entry:
   %mul = mul nsw i8 %y, %x
   ret i8 %mul
 }
 
 define i8 @MUL_CHAR_I(i8 %x) {
 ; CHECK-LABEL: MUL_CHAR_I:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movih32 a1, 65535
-; CHECK-NEXT:    ori32 a1, a1, 65533
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    ixh32 a0, a0, a0
+; CHECK-NEXT:    movi16 a1, 0
+; CHECK-NEXT:    subu16 a0, a1, a0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: MUL_CHAR_I:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a3, a1, 16
-; GENERIC-NEXT:    or16 a3, a2
-; GENERIC-NEXT:    lsli16 a1, a1, 8
-; GENERIC-NEXT:    or16 a1, a3
-; GENERIC-NEXT:    movi16 a2, 253
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    mult16 a0, a2
+; GENERIC-NEXT:    lsli16 a1, a0, 1
+; GENERIC-NEXT:    addu16 a0, a1, a0
+; GENERIC-NEXT:    movi16 a1, 0
+; GENERIC-NEXT:    subu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %mul = mul nsw i8 %x, -3
   ret i8 %mul
 }
 
 define i32 @udivRR(i32 %x, i32 %y) {

 ; GENERIC-NEXT:    mov16 a1, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI25_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i32 %y, %x
   ret i32 %udiv
 }
 
 define i32 @udivRI(i32 %x) {

 ; GENERIC-NEXT:    movi16 a1, 10
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI26_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i32 %x, 10
   ret i32 %udiv
 }
 
 define i32 @udivRI_X(i32 %x) {

 ; GENERIC-NEXT:    lrw32 a2, [.LCPI27_0]
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI27_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i32 %x, 4097
   ret i32 %udiv
 }
 
 define i16 @UDIV_SHORT(i16 %x, i16 %y) {

 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    ld16.w l0, (sp, 4) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 8
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI28_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i16 %y, %x
   ret i16 %udiv
 }
 
 define i16 @UDIV_SHORT_I(i16 %x) {

 ; GENERIC-NEXT:    mov16 a0, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI30_0:
 ; GENERIC-NEXT:    .long __udivsi3
 entry:
   %udiv = udiv  i8 %y, %x
   ret i8 %udiv
 }
 
 define i8 @UDIV_CHAR_I(i8 %x) {

 ; GENERIC-NEXT:    mov16 a1, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI32_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i32 %y, %x
   ret i32 %sdiv
 }
 
 define i32 @sdivRI(i32 %x) {

 ; GENERIC-NEXT:    movi16 a1, 10
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI33_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i32 %x, 10
   ret i32 %sdiv
 }
 
 define i32 @sdivRI_X(i32 %x) {

 ; GENERIC-NEXT:    lrw32 a2, [.LCPI34_0]
 ; GENERIC-NEXT:    jsr16 a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI34_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i32 %x, 4097
   ret i32 %sdiv
 }
 
 define i16 @SDIV_SHORT(i16 %x, i16 %y) {

 ; GENERIC-NEXT:    mov16 a0, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI35_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i16 %y, %x
   ret i16 %sdiv
 }
 
 define i16 @SDIV_SHORT_I(i16 %x) {

 ; GENERIC-NEXT:    mov16 a0, a2
 ; GENERIC-NEXT:    jsr16 a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 ; GENERIC-NEXT:    .p2align 1
 ; GENERIC-NEXT:  # %bb.1:
-; GENERIC-NEXT:    .p2align 2
+; GENERIC-NEXT:    .p2align 2, 0x0
 ; GENERIC-NEXT:  .LCPI37_0:
 ; GENERIC-NEXT:    .long __divsi3
 entry:
   %sdiv = sdiv  i8 %y, %x
   ret i8 %sdiv
 }
 
 define i8 @SDIV_CHAR_I(i8 %x) {

llvm/test/CodeGen/CSKY/mul-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 < %s -mtriple=csky | FileCheck %s
 ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
 
 ;; This file shows if a multiplication can be simplified to an addition/subtraction
 ;; of left shifts.
 
 define i32 @mul_i32_4097(i32 %x) {
 ; CHECK-LABEL: mul_i32_4097:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi32 a1, 4097
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 12
+; CHECK-NEXT:    addu16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i32_4097:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 0
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a1, a1, 16
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    movi16 a2, 16
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    movi16 a1, 1
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    addu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i32 %x, 4097
   ret i32 %y
 }
 
 define i32 @mul_i32_4095(i32 %x) {
 ; CHECK-LABEL: mul_i32_4095:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi32 a1, 4095
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 12
+; CHECK-NEXT:    subu16 a0, a1, a0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i32_4095:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 0
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a1, a1, 16
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    movi16 a2, 15
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    subu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i32 %x, 4095
   ret i32 %y
 }
 
 define i32 @mul_i32_minus_4095(i32 %x) {
 ; CHECK-LABEL: mul_i32_minus_4095:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movih32 a1, 65535
-; CHECK-NEXT:    ori32 a1, a1, 61441
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 12
+; CHECK-NEXT:    subu16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i32_minus_4095:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a1, a1, 16
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    movi16 a2, 240
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    movi16 a1, 1
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    subu16 a0, a0, a1
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i32 %x, -4095
   ret i32 %y
 }
 
 define i16 @mul_i16_4097(i16 %x) {
 ; CHECK-LABEL: mul_i16_4097:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi32 a1, 4097
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 12
+; CHECK-NEXT:    addu16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i16_4097:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 0
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a1, a1, 16
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    movi16 a2, 16
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    movi16 a1, 1
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    addu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i16 %x, 4097
   ret i16 %y
 }
 
 define i16 @mul_i16_4095(i16 %x) {
 ; CHECK-LABEL: mul_i16_4095:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi32 a1, 4095
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 12
+; CHECK-NEXT:    subu16 a0, a1, a0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i16_4095:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 0
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a1, a1, 16
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    movi16 a2, 15
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    subu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i16 %x, 4095
   ret i16 %y
 }
 
 define i16 @mul_i16_minus_4095(i16 %x) {
 ; CHECK-LABEL: mul_i16_minus_4095:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movih32 a1, 65535
-; CHECK-NEXT:    ori32 a1, a1, 61441
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 12
+; CHECK-NEXT:    subu16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i16_minus_4095:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a1, a1, 16
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    movi16 a2, 240
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    movi16 a1, 1
-; GENERIC-NEXT:    or16 a1, a2
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    subu16 a0, a0, a1
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i16 %x, -4095
   ret i16 %y
 }
 
 define i8 @mul_i8_65(i8 %x) {
 ; CHECK-LABEL: mul_i8_65:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi16 a1, 65
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 6
+; CHECK-NEXT:    addu16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i8_65:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 65
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 6
+; GENERIC-NEXT:    addu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i8 %x, 65
   ret i8 %y
 }
 
 define i8 @mul_i8_63(i8 %x) {
 ; CHECK-LABEL: mul_i8_63:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movi16 a1, 63
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 6
+; CHECK-NEXT:    subu16 a0, a1, a0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i8_63:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 63
-; GENERIC-NEXT:    mult16 a0, a1
+; GENERIC-NEXT:    lsli16 a1, a0, 6
+; GENERIC-NEXT:    subu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i8 %x, 63
   ret i8 %y
 }
 
 define i8 @mul_i8_minus_63(i8 %x) {
 ; CHECK-LABEL: mul_i8_minus_63:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movih32 a1, 65535
-; CHECK-NEXT:    ori32 a1, a1, 65473
-; CHECK-NEXT:    mult16 a0, a1
+; CHECK-NEXT:    lsli16 a1, a0, 6
+; CHECK-NEXT:    subu16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i8_minus_63:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a3, a1, 16
-; GENERIC-NEXT:    or16 a3, a2
-; GENERIC-NEXT:    lsli16 a1, a1, 8
-; GENERIC-NEXT:    or16 a1, a3
-; GENERIC-NEXT:    movi16 a2, 193
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    mult16 a0, a2
+; GENERIC-NEXT:    lsli16 a1, a0, 6
+; GENERIC-NEXT:    subu16 a0, a0, a1
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i8 %x, -63
   ret i8 %y
 }
 
 define i32 @mul_i32_minus_4097(i32 %x) {
 ; CHECK-LABEL: mul_i32_minus_4097:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movih32 a1, 65535
 ; CHECK-NEXT:    ori32 a1, a1, 61439
 ; CHECK-NEXT:    mult16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i32_minus_4097:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a3, a1, 16
-; GENERIC-NEXT:    or16 a3, a2
-; GENERIC-NEXT:    movi16 a2, 239
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a3
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    mult16 a0, a2
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    addu16 a0, a1, a0
+; GENERIC-NEXT:    movi16 a1, 0
+; GENERIC-NEXT:    subu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i32 %x, -4097
   ret i32 %y
 }
 
 define i16 @mul_i16_minus_4097(i16 %x) {
 ; CHECK-LABEL: mul_i16_minus_4097:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movih32 a1, 65535
 ; CHECK-NEXT:    ori32 a1, a1, 61439
 ; CHECK-NEXT:    mult16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i16_minus_4097:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a3, a1, 16
-; GENERIC-NEXT:    or16 a3, a2
-; GENERIC-NEXT:    movi16 a2, 239
-; GENERIC-NEXT:    lsli16 a2, a2, 8
-; GENERIC-NEXT:    or16 a2, a3
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    mult16 a0, a2
+; GENERIC-NEXT:    lsli16 a1, a0, 12
+; GENERIC-NEXT:    addu16 a0, a1, a0
+; GENERIC-NEXT:    movi16 a1, 0
+; GENERIC-NEXT:    subu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i16 %x, -4097
   ret i16 %y
 }
 
 define i8 @mul_i8_minus_65(i8 %x) {
 ; CHECK-LABEL: mul_i8_minus_65:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movih32 a1, 65535
 ; CHECK-NEXT:    ori32 a1, a1, 65471
 ; CHECK-NEXT:    mult16 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: mul_i8_minus_65:
 ; GENERIC:       # %bb.0: # %entry
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
-; GENERIC-NEXT:    movi16 a1, 255
-; GENERIC-NEXT:    lsli16 a2, a1, 24
-; GENERIC-NEXT:    lsli16 a3, a1, 16
-; GENERIC-NEXT:    or16 a3, a2
-; GENERIC-NEXT:    lsli16 a1, a1, 8
-; GENERIC-NEXT:    or16 a1, a3
-; GENERIC-NEXT:    movi16 a2, 191
-; GENERIC-NEXT:    or16 a2, a1
-; GENERIC-NEXT:    mult16 a0, a2
+; GENERIC-NEXT:    lsli16 a1, a0, 6
+; GENERIC-NEXT:    addu16 a0, a1, a0
+; GENERIC-NEXT:    movi16 a1, 0
+; GENERIC-NEXT:    subu16 a0, a1, a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %y = mul nsw i8 %x, -65
   ret i8 %y
 }
 
 ;; This case can not be optimized, due to the data type exceeds.
 define i64 @mul_i64_4097(i64 %x) {
 ; CHECK-LABEL: mul_i64_4097:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subi16 sp, sp, 4
 ; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset lr, -4
 ; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    lrw32 t0, [.LCPI12_0]