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Differential D152129

[AVR][NFC][test] Supplement more tests of 8-bit rotation
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Authored by benshi001 on Jun 5 2023, 1:43 AM.

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Reviewers
aykevl
Patryk27
jacquesguan
Commits
rGb1f0cb89c1d0: [AVR][NFC][test] Supplement more tests of 8-bit rotation

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Event Timeline

benshi001 created this revision.Jun 5 2023, 1:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 5 2023, 1:43 AM
Herald added subscribers: Jim, dylanmckay. · View Herald Transcript
benshi001 requested review of this revision.Jun 5 2023, 1:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 5 2023, 1:43 AM
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Patryk27 accepted this revision.Jun 5 2023, 1:46 AM
This revision is now accepted and ready to land.Jun 5 2023, 1:46 AM
benshi001 added a child revision: D152130: [AVR] Optimize 8-bit rotation when rotation bits >= 4.Jun 5 2023, 1:50 AM
jacquesguan accepted this revision.Jun 5 2023, 2:09 AM
Harbormaster completed remote builds in B236539: Diff 528313.Jun 5 2023, 2:24 AM
benshi001 updated this revision to Diff 528334.Jun 5 2023, 2:41 AM
Harbormaster completed remote builds in B236558: Diff 528334.Jun 5 2023, 3:28 AM
Closed by commit rGb1f0cb89c1d0: [AVR][NFC][test] Supplement more tests of 8-bit rotation (authored by benshi001). · Explain WhyJun 5 2023, 8:24 PM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGb1f0cb89c1d0: [AVR][NFC][test] Supplement more tests of 8-bit rotation.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AVR/
112 lines

Diff 528334

llvm/test/CodeGen/AVR/rotate.ll

Show All 21 Lines
; CHECK-NEXT: lsl r24 ; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1 ; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
start: start:
%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3) %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
ret i8 %0 ret i8 %0
} }
define i8 @rotl8_5(i8 %x) {
; CHECK-LABEL: rotl8_5:
; CHECK: ; %bb.0: ; %start
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: ret
start:
%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 5)
ret i8 %0
}
define i8 @rotl8_7(i8 %x) {
; CHECK-LABEL: rotl8_7:
; CHECK: ; %bb.0: ; %start
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: ret
start:
%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 7)
ret i8 %0
}
define i8 @rotl8_dyn(i8 %x, i8 %y) { define i8 @rotl8_dyn(i8 %x, i8 %y) {
; CHECK-LABEL: rotl8_dyn: ; CHECK-LABEL: rotl8_dyn:
; CHECK: ; %bb.0: ; %start ; CHECK: ; %bb.0: ; %start
; CHECK-NEXT: andi r22, 7 ; CHECK-NEXT: andi r22, 7
; CHECK-NEXT: dec r22 ; CHECK-NEXT: dec r22
; CHECK-NEXT: brmi .LBB2_2 ; CHECK-NEXT: brmi .LBB4_2
; CHECK-NEXT: .LBB2_1: ; %start ; CHECK-NEXT: .LBB4_1: ; %start
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lsl r24 ; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1 ; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: dec r22 ; CHECK-NEXT: dec r22
; CHECK-NEXT: brpl .LBB2_1 ; CHECK-NEXT: brpl .LBB4_1
; CHECK-NEXT: .LBB2_2: ; %start ; CHECK-NEXT: .LBB4_2: ; %start
; CHECK-NEXT: ret ; CHECK-NEXT: ret
start: start:
%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y) %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
ret i8 %0 ret i8 %0
} }
define i8 @rotr8_1(i8 %x) { define i8 @rotr8_1(i8 %x) {
; CHECK-LABEL: rotr8_1: ; CHECK-LABEL: rotr8_1:
Show All 20 Lines
; CHECK-NEXT: ror r24 ; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7 ; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: ret ; CHECK-NEXT: ret
start: start:
%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3) %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
ret i8 %0 ret i8 %0
} }
define i8 @rotr8_5(i8 %x) {
; CHECK-LABEL: rotr8_5:
; CHECK: ; %bb.0: ; %start
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: ret
start:
%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 5)
ret i8 %0
}
define i8 @rotr8_7(i8 %x) {
; CHECK-LABEL: rotr8_7:
; CHECK: ; %bb.0: ; %start
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: ret
start:
%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 7)
ret i8 %0
}
define i8 @rotr8_dyn(i8 %x, i8 %y) { define i8 @rotr8_dyn(i8 %x, i8 %y) {
; CHECK-LABEL: rotr8_dyn: ; CHECK-LABEL: rotr8_dyn:
; CHECK: ; %bb.0: ; %start ; CHECK: ; %bb.0: ; %start
; CHECK-NEXT: andi r22, 7 ; CHECK-NEXT: andi r22, 7
; CHECK-NEXT: dec r22 ; CHECK-NEXT: dec r22
; CHECK-NEXT: brmi .LBB5_2 ; CHECK-NEXT: brmi .LBB9_2
; CHECK-NEXT: .LBB5_1: ; %start ; CHECK-NEXT: .LBB9_1: ; %start
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: bst r24, 0 ; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24 ; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7 ; CHECK-NEXT: bld r24, 7
; CHECK-NEXT: dec r22 ; CHECK-NEXT: dec r22
; CHECK-NEXT: brpl .LBB5_1 ; CHECK-NEXT: brpl .LBB9_1
; CHECK-NEXT: .LBB5_2: ; %start ; CHECK-NEXT: .LBB9_2: ; %start
; CHECK-NEXT: ret ; CHECK-NEXT: ret
start: start:
%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y) %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
ret i8 %0 ret i8 %0
} }
define i16 @rotl16(i16 %x) { define i16 @rotl16(i16 %x) {
; CHECK-LABEL: rotl16: ; CHECK-LABEL: rotl16:
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