[M68k][MC] Add support for 32 bit register-register multiply/divide

[ids1024]

Summary

Previously when targeting 68020+, instruction selection attempted to
emit a 32-bit register-register multiplication, but failed at
instruction selection. With this, it succeeds.

[myhsu]

Thank you for adding this. Could you add some codegen tests (i.e. LLVM IR -> assembly)?

[ids1024]

Add codegen test, and make compiler emit 32-bit div on 68020+.

[myhsu]

LGTM with minor comments. Thanks!
Also, since now there are several LLVM patches under your belt, you might want to obtain a commit access. Let me know if you need any help on that!

llvm/lib/Target/M68k/M68kInstrArithmetic.td

637

nit: the double quotes are not necessary. Ditto for other occurrences in this patch

[ids1024]

Remove unneeded uses of "

llvm/lib/Target/M68k/M68kISelLowering.cpp

M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
   // We don't accept any truncstore of integer registers.
   setTruncStoreAction(MVT::i64, MVT::i32, Expand);
   setTruncStoreAction(MVT::i64, MVT::i16, Expand);
   setTruncStoreAction(MVT::i64, MVT::i8, Expand);
   setTruncStoreAction(MVT::i32, MVT::i16, Expand);
   setTruncStoreAction(MVT::i32, MVT::i8, Expand);
   setTruncStoreAction(MVT::i16, MVT::i8, Expand);
 
-  setOperationAction(ISD::MUL, MVT::i8, Promote);
-  setOperationAction(ISD::MUL, MVT::i16, Legal);
+  setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote);
+  setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal);
   if (Subtarget.atLeastM68020())
-    setOperationAction(ISD::MUL, MVT::i32, Legal);
+    setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal);
   else
-    setOperationAction(ISD::MUL, MVT::i32, LibCall);
+    setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall);
   setOperationAction(ISD::MUL, MVT::i64, LibCall);
 
   for (auto OP :
-       {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM,
+       {ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM,
         ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
     setOperationAction(OP, MVT::i8, Promote);
     setOperationAction(OP, MVT::i16, Legal);
     setOperationAction(OP, MVT::i32, LibCall);
   }
 
   for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
     setOperationAction(OP, MVT::i8, Expand);

llvm/lib/Target/M68k/M68kInstrArithmetic.td

class MxDiMuOp_DD<string MN, bits<4> CMD, bit SIGNED = false,
   let Inst = (descend CMD,
     // REGISTER
     (operand "$dst", 3),
     !if(SIGNED, 0b111, 0b011),
     /*MODE*/0b000, /*REGISTER*/(operand "$opd", 3)
   );
 }
 
+// $dreg <- $dreg op $dreg
+class MxDiMuOp_DD_Long<string MN, bits<10> CMD, bit SIGNED = false>
+    : MxInst<(outs MxDRD32:$dst), (ins MxDRD32:$src, MxDRD32:$opd), MN#"\t$opd, $dst", []> {
+  let Inst = (ascend
+    (descend CMD,
+      /*MODE*/0b000, /*REGISTER*/(operand "$opd", 3)),
+    (descend 0b0,
+      // REGISTER
+      (operand "$dst", 3),
+      !if(SIGNED, 0b1, 0b0),
+      /*SIZE*/0b0, 0b0000000,
+      // Dr REGISTER
+      0b000)
+  );
+}
+
 // $reg <- $reg op $imm
 class MxDiMuOp_DI<string MN, bits<4> CMD, bit SIGNED = false,
                   MxOperand DST, MxOperand OPD>
     : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", []> {
   // FIXME: Support immediates with different widths.
   defvar ImmEnc = MxEncAddrMode_i<"opd", 16>;
   let Inst = (ascend
     (descend CMD,
multiclass MxDiMuOp<string MN, bits<4> CMD, bit isComm = 0> {
   }
 
   def "S"#NAME#"d32i16" : MxDiMuOp_DI<MN#"s", CMD, /*SIGNED*/true, MxDRD32, Mxi16imm>;
   def "U"#NAME#"d32i16" : MxDiMuOp_DI<MN#"u", CMD, /*SIGNED*/false, MxDRD32, Mxi16imm>;
 }
 
 defm DIV : MxDiMuOp<"div", 0x8>;
 
+def SDIVd32d32 : MxDiMuOp_DD_Long<"divs.l", 0x131, /*SIGNED*/true>;
+def UDIVd32d32 : MxDiMuOp_DD_Long<"divu.l", 0x131, /*SIGNED*/false>;
+
 // This is used to cast immediates to 16-bits for operations which don't
 // support smaller immediate sizes.
 def as_i16imm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
 }]>;
 
 // RR i8
 def : Pat<(sdiv i8:$dst, i8:$opd),
def : Pat<(srem i16:$dst, i16:$opd),
              MxSubRegIndex16Lo)>;
 
 def : Pat<(urem i16:$dst, i16:$opd),
           (EXTRACT_SUBREG
             (LSR32di (LSR32di (UDIVd32d16 (MOVZXd32d16 $dst), $opd), 8), 8),
              MxSubRegIndex16Lo)>;
 
 
+// RR i32
+def : Pat<(sdiv i32:$dst, i32:$opd), (SDIVd32d32 $dst, $opd)>;
+
+def : Pat<(udiv i32:$dst, i32:$opd), (UDIVd32d32 $dst, $opd)>;
+
+
 // RI i8
 def : Pat<(sdiv i8:$dst, MximmSExt8:$opd),
           (EXTRACT_SUBREG
             (SDIVd32i16 (MOVSXd32d8 $dst), (as_i16imm $opd)),
              MxSubRegIndex8Lo)>;
 
 def : Pat<(udiv i8:$dst, MximmSExt8:$opd),
           (EXTRACT_SUBREG

 def : Pat<(urem i16:$dst, MximmSExt16:$opd),
           (EXTRACT_SUBREG
             (LSR32di (LSR32di (UDIVd32i16 (MOVZXd32d16 $dst), imm:$opd), 8), 8),
              MxSubRegIndex16Lo)>;
 
 
 defm MUL : MxDiMuOp<"mul", 0xC, 1>;
 
+def SMULd32d32 : MxDiMuOp_DD_Long<"muls.l", 0x130, /*SIGNED*/true>;
+def UMULd32d32 : MxDiMuOp_DD_Long<"mulu.l", 0x130, /*SIGNED*/false>;
+
 // RR
 def : Pat<(mul i16:$dst, i16:$opd),
           (EXTRACT_SUBREG
             (SMULd32d16 (MOVXd32d16 $dst), $opd),
              MxSubRegIndex16Lo)>;
 
 def : Pat<(mulhs i16:$dst, i16:$opd),
           (EXTRACT_SUBREG
             (ASR32di (ASR32di (SMULd32d16 (MOVXd32d16 $dst), $opd), 8), 8),
              MxSubRegIndex16Lo)>;
 
 def : Pat<(mulhu i16:$dst, i16:$opd),
           (EXTRACT_SUBREG
             (LSR32di (LSR32di (UMULd32d16 (MOVXd32d16 $dst), $opd), 8), 8),
              MxSubRegIndex16Lo)>;
 
+def : Pat<(mul i32:$dst, i32:$opd), (SMULd32d32 $dst, $opd)>;
+
 
 // RI
 def : Pat<(mul i16:$dst, MximmSExt16:$opd),
           (EXTRACT_SUBREG
             (SMULd32i16 (MOVXd32d16 $dst), imm:$opd),
              MxSubRegIndex16Lo)>;
 
 def : Pat<(mulhs i16:$dst, MximmSExt16:$opd),

llvm/test/CodeGen/M68k/Arith/mul_div_32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=m68k-linux --mcpu M68020 | FileCheck %s
+
+define i32 @mul32(i32 %A, i32 %B) {
+; CHECK-LABEL: mul32:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0:
+; CHECK-NEXT:    move.l (8,%sp), %d1
+; CHECK-NEXT:    move.l (4,%sp), %d0
+; CHECK-NEXT:    muls.l %d1, %d0
+; CHECK-NEXT:    rts
+    %mul = mul i32 %A, %B
+    ret i32 %mul
+}
+
+define i32 @sdiv_32(i32 %A, i32 %B) {
+; CHECK-LABEL: sdiv_32:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0:
+; CHECK-NEXT:    move.l (8,%sp), %d1
+; CHECK-NEXT:    move.l (4,%sp), %d0
+; CHECK-NEXT:    divs.l %d1, %d0
+; CHECK-NEXT:    rts
+    %div = sdiv i32 %A, %B
+    ret i32 %div
+}
+
+define i32 @udiv32(i32 %A, i32 %B) {
+; CHECK-LABEL: udiv32:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0:
+; CHECK-NEXT:    move.l (8,%sp), %d1
+; CHECK-NEXT:    move.l (4,%sp), %d0
+; CHECK-NEXT:    divu.l %d1, %d0
+; CHECK-NEXT:    rts
+    %div = udiv i32 %A, %B
+    ret i32 %div
+}

llvm/test/MC/M68k/Arith/Classes/MxDiMu.s

 ; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
 
 ; CHECK:      divs  %d1, %d0
 ; CHECK-SAME: encoding: [0x81,0xc1]
 divs  %d1, %d0
 ; CHECK:      divu  %d1, %d0
 ; CHECK-SAME: encoding: [0x80,0xc1]
 divu  %d1, %d0
 ; CHECK:      divs  #0, %d0
 ; CHECK-SAME: encoding: [0x81,0xfc,0x00,0x00]
 divs  #0, %d0
 ; CHECK:      divu  #-1, %d0
 ; CHECK-SAME: encoding: [0x80,0xfc,0xff,0xff]
 divu  #-1, %d0
+; CHECK:  divs.l  %d1, %d0
+; CHECK-SAME: encoding: [0x4c,0x41,0x08,0x00]
+divs.l  %d1, %d0
+; CHECK:  divu.l  %d1, %d0
+; CHECK-SAME: encoding: [0x4c,0x41,0x00,0x00]
+divu.l  %d1, %d0
 ; CHECK:      muls  %d1, %d0
 ; CHECK-SAME: encoding: [0xc1,0xc1]
 muls  %d1, %d0
 ; CHECK:      mulu  %d1, %d0
 ; CHECK-SAME: encoding: [0xc0,0xc1]
 mulu  %d1, %d0
 ; CHECK:      muls  #0, %d0
 ; CHECK-SAME: encoding: [0xc1,0xfc,0x00,0x00]
 muls  #0, %d0
 ; CHECK:      mulu  #-1, %d0
 ; CHECK-SAME: encoding: [0xc0,0xfc,0xff,0xff]
 mulu  #-1, %d0
+; CHECK:      muls.l  %d1, %d0
+; CHECK-SAME: encoding: [0x4c,0x01,0x08,0x00]
+muls.l  %d1, %d0
+; CHECK:      mulu.l  %d1, %d0
+; CHECK-SAME: encoding: [0x4c,0x01,0x00,0x00]
+mulu.l  %d1, %d0