[InstCombine] precommit test for D152068(NFC)

[khei4]

Summary

precommit test for D152068

[nikic]

llvm/test/Transforms/InstCombine/addsub-constant-folding.ll

135 ↗

(On Diff #528182)

For tests with overflowing constants, I'd recommend using i8 as it's easier to see what overflows and what doesn't at a glance.

151 ↗

(On Diff #528182)

Can also add nuw here to check that the right attribute presence is checked.

175 ↗

(On Diff #528182)

It would be good to have a test with non-splat vector constants (one with and one without overflow), as this fold supports them.

[khei4]

llvm/test/Transforms/InstCombine/addsub-constant-folding.ll

175 ↗

(On Diff #528182)

Thank you for a good catch! I could find currently, i.e. C = <i8 1, i8 3>, C2 = <i8 -127, i8 -125>, bool WillNotSOV = willNotOverflowSignedSub(C, C2, I); would be false because computeOverflowForSignedSub can't check correctly, but each vector's maximum and minimum element range??

[nikic]

llvm/test/Transforms/InstCombine/addsub-constant-folding.ll

175 ↗

(On Diff #528182)

In that case, just leave a TODO in the test.

[khei4]

add splat vector tests

[khei4]

fix typo

[khei4]

Add nuw case and non-splat vector cases

[khei4]

fix wrong diff upload

llvm/test/Transforms/InstCombine/add.ll

 ; CHECK-NEXT:    [[C:%.*]] = sub i8 16, [[A:%.*]]
 ; CHECK-NEXT:    ret i8 [[C]]
 ;
   %B = xor i8 %A, -1
   %C = add i8 %B, 17
   ret i8 %C
 }
 
+; ~X + -127 and (-128) - X with nsw are equally poisonous
+define i8 @test18_nsw(i8 %A) {
+; CHECK-LABEL: @test18_nsw(
+; CHECK-NEXT:    [[C:%.*]] = sub i8 -128, [[A:%.*]]
+; CHECK-NEXT:    ret i8 [[C]]
+;
+  %B = xor i8 %A, -1
+  %C = add nsw i8 %B, -127
+  ret i8 %C
+}
+
+; nuw couldn't propagate as nsw is.
+define i8 @test18_nuw(i8 %A) {
+; CHECK-LABEL: @test18_nuw(
+; CHECK-NEXT:    [[C:%.*]] = sub i8 -128, [[A:%.*]]
+; CHECK-NEXT:    ret i8 [[C]]
+;
+  %B = xor i8 %A, -1
+  %C = add nuw i8 %B, -127
+  ret i8 %C
+}
+
+; 127 - X with nsw will be more poisonous than ~X + -128 with nsw. (see X = -1)
+define i8 @test18_nsw_overflow(i8 %A) {
+; CHECK-LABEL: @test18_nsw_overflow(
+; CHECK-NEXT:    [[C:%.*]] = sub i8 127, [[A:%.*]]
+; CHECK-NEXT:    ret i8 [[C]]
+;
+  %B = xor i8 %A, -1
+  %C = add nsw i8 %B, -128
+  ret i8 %C
+}
+
 define <2 x i64> @test18vec(<2 x i64> %A) {
 ; CHECK-LABEL: @test18vec(
 ; CHECK-NEXT:    [[ADD:%.*]] = sub <2 x i64> <i64 1, i64 2>, [[A:%.*]]
 ; CHECK-NEXT:    ret <2 x i64> [[ADD]]
 ;
   %xor = xor <2 x i64> %A, <i64 -1, i64 -1>
   %add = add <2 x i64> %xor, <i64 2, i64 3>
   ret <2 x i64> %add
 }
 
+define <2 x i8> @test18vec_nsw(<2 x i8> %A) {
+; CHECK-LABEL: @test18vec_nsw(
+; CHECK-NEXT:    [[C:%.*]] = sub <2 x i8> <i8 -126, i8 -125>, [[A:%.*]]
+; CHECK-NEXT:    ret <2 x i8> [[C]]
+;
+  %B = xor <2 x i8> %A, <i8 -1, i8 -1>
+  %C = add nsw <2 x i8> %B, <i8 -125, i8 -124>
+  ret <2 x i8> %C
+}
+
+; TODO: fix ValueTracking overflow check for non-splat vector
+define <2 x i8> @test18vec_nsw_false(<2 x i8> %A) {
+; CHECK-LABEL: @test18vec_nsw_false(
+; CHECK-NEXT:    [[C:%.*]] = sub <2 x i8> <i8 -128, i8 -127>, [[A:%.*]]
+; CHECK-NEXT:    ret <2 x i8> [[C]]
+;
+  %B = xor <2 x i8> %A, <i8 -1, i8 -1>
+  %C = add nsw <2 x i8> %B, <i8 -127, i8 -126>
+  ret <2 x i8> %C
+}
+
+
+define <2 x i8> @test18vec_nuw(<2 x i8> %A) {
+; CHECK-LABEL: @test18vec_nuw(
+; CHECK-NEXT:    [[C:%.*]] = sub <2 x i8> <i8 -128, i8 -127>, [[A:%.*]]
+; CHECK-NEXT:    ret <2 x i8> [[C]]
+;
+  %B = xor <2 x i8> %A, <i8 -1, i8 -1>
+  %C = add nuw <2 x i8> %B, <i8 -127, i8 -126>
+  ret <2 x i8> %C
+}
+
+define <2 x i8> @test18vec_nsw_overflow(<2 x i8> %A) {
+; CHECK-LABEL: @test18vec_nsw_overflow(
+; CHECK-NEXT:    [[C:%.*]] = sub <2 x i8> <i8 -128, i8 127>, [[A:%.*]]
+; CHECK-NEXT:    ret <2 x i8> [[C]]
+;
+  %B = xor <2 x i8> %A, <i8 -1, i8 -1>
+  %C = add nsw <2 x i8> %B, <i8 -127, i8 -128>
+  ret <2 x i8> %C
+}
+
 define i32 @test19(i1 %C) {
 ; CHECK-LABEL: @test19(
 ; CHECK-NEXT:    [[V:%.*]] = select i1 [[C:%.*]], i32 1123, i32 133
 ; CHECK-NEXT:    ret i32 [[V]]
 ;
   %A = select i1 %C, i32 1000, i32 10
   %V = add i32 %A, 123
   ret i32 %V