[X86] Don't crash on instruction prefetch intrinsics without PREFETCHI support.

[craig.topper]

Summary

Instead of failing to select during isel, drop the intrinsic in
lowering.

Fixes PR62839.

[pengfei]

We have limited it in the FE. I was considering if we should lower it to other prefetch instructions if prefetchi is not supported. Some people have concern prefetching to data cache may not help with execution. Not emitting instruction seems good, thanks!

llvm/lib/Target/X86/X86ISelLowering.cpp

for (auto VT : { MVT::i32, MVT::i64 }) {
     if (VT == MVT::i64 && !Subtarget.is64Bit())
       continue;
     setOperationAction(ISD::SHL_PARTS, VT, Custom);
     setOperationAction(ISD::SRA_PARTS, VT, Custom);
     setOperationAction(ISD::SRL_PARTS, VT, Custom);
   }
 
   if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow())
-    setOperationAction(ISD::PREFETCH      , MVT::Other, Legal);
+    setOperationAction(ISD::PREFETCH      , MVT::Other, Custom);
 
   setOperationAction(ISD::ATOMIC_FENCE  , MVT::Other, Custom);
 
   // Expand certain atomics
   for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
     setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
     setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
     setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
static SDValue LowerCVTPS2PH(SDValue Op, SelectionDAG &DAG) {
   EVT LoVT, HiVT;
   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
   SDValue RC = Op.getOperand(1);
   Lo = DAG.getNode(X86ISD::CVTPS2PH, dl, LoVT, Lo, RC);
   Hi = DAG.getNode(X86ISD::CVTPS2PH, dl, HiVT, Hi, RC);
   return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
 }
 
+static SDValue LowerPREFETCH(SDValue Op, const X86Subtarget &Subtarget,
+                             SelectionDAG &DAG) {
+  unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
+
+  // We don't support non-data prefetch without PREFETCHI.
+  // Just preserve the chain.
+  if (!IsData && !Subtarget.hasPREFETCHI())
+    return Op.getOperand(0);
+
+  return Op;
+}
+
 static StringRef getInstrStrFromOpNo(const SmallVectorImpl<StringRef> &AsmStrs,
                                      unsigned OpNo) {
   const APInt Operand(32, OpNo);
   std::string OpNoStr = llvm::toString(Operand, 10, false);
   std::string Str(" $");
 
   std::string OpNoStr1(Str + OpNoStr);             // e.g. " $1" (OpNo=1)
   std::string OpNoStr2(Str + "{" + OpNoStr + ":"); // With modifier, e.g. ${1:P}
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::MLOAD:              return LowerMLOAD(Op, Subtarget, DAG);
   case ISD::MSTORE:             return LowerMSTORE(Op, Subtarget, DAG);
   case ISD::MGATHER:            return LowerMGATHER(Op, Subtarget, DAG);
   case ISD::MSCATTER:           return LowerMSCATTER(Op, Subtarget, DAG);
   case ISD::GC_TRANSITION_START:
   case ISD::GC_TRANSITION_END:  return LowerGC_TRANSITION(Op, DAG);
   case ISD::ADDRSPACECAST:      return LowerADDRSPACECAST(Op, DAG);
   case X86ISD::CVTPS2PH:        return LowerCVTPS2PH(Op, DAG);
+  case ISD::PREFETCH:           return LowerPREFETCH(Op, Subtarget, DAG);
   }
 }
 
 /// Replace a node with an illegal result type with a new node built out of
 /// custom code.
 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
                                            SmallVectorImpl<SDValue>&Results,
                                            SelectionDAG &DAG) const {

llvm/test/CodeGen/X86/prefetchi.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchi | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=NOPREFETCHI
 
 define dso_local void @t(ptr %ptr) nounwind  {
 ; CHECK-LABEL: t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    prefetchit1 (%rdi)
 ; CHECK-NEXT:    prefetchit0 (%rdi)
 ; CHECK-NEXT:    prefetchit1 t(%rip)
 ; CHECK-NEXT:    prefetchit0 ext(%rip)
 ; CHECK-NEXT:    retq
+;
+; NOPREFETCHI-LABEL: t:
+; NOPREFETCHI:       # %bb.0: # %entry
+; NOPREFETCHI-NEXT:    retq
 entry:
   tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 2, i32 0)
   tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 3, i32 0)
   tail call void @llvm.prefetch(ptr @t,   i32 0, i32 2, i32 0)
   tail call void @llvm.prefetch(ptr @ext, i32 0, i32 3, i32 0)
   ret void
 }
 
 declare dso_local void @ext() nounwind
 declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind