[Hexagon] Flip subreg bit for reverse pairs hvx .new

[quic-akaryaki]

Summary

In .new instructions, the upper vector of a reverse pair (e.g. V4 in
V4:5) should be referenced with an odd sss value.

[kparzysz]

Thanks!

[quic-akaryaki]

The test fails so far.

[quic-akaryaki]

Add explicit version to objdump.

[quic-akaryaki]

@kparzysz @bcain If this looks good, can you accept and merge it? Thanks.

llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

     } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
       unsigned Producer =
           HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
 
       if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
         const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
         const unsigned ProdPairIndex =
             Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
+        if (Rev)
+          SubregBit = !SubregBit;
         Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
       } else if (SubregBit)
         // Hexagon PRM 10.11 New-value operands
         // Nt[0] is reserved and should always be encoded as zero.
         return MCDisassembler::Fail;
       assert(Producer != Hexagon::NoRegister);
       MCO.setReg(Producer);
     } else

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

   Operand.setImm(Operand.getImm() | outerLoopMask);
 }
 
 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
                                             unsigned Producer,
                                             unsigned Producer2) {
   // If we're a single vector consumer of a double producer, set subreg bit
   // based on if we're accessing the lower or upper register component
-  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
-    return (Consumer - Hexagon::V0) & 0x1;
+  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
+    unsigned Rev = IsReverseVecRegPair(Producer);
+    return ((Consumer - Hexagon::V0) & 0x1) ^ Rev;
+  }
   if (Producer2 != Hexagon::NoRegister)
     return Consumer == Producer;
   return 0;
 }
 
 bool HexagonMCInstrInfo::LoopNeedsPadding(MCInst const &MCB) {
   return (
       (HexagonMCInstrInfo::isInnerLoop(MCB) &&

llvm/test/MC/Hexagon/hvx-nv-pair-reverse.s

+# RUN: llvm-mc -arch=hexagon -mv69 -mhvx -filetype=obj %s | \
+# RUN:   llvm-objdump --arch=hexagon --mcpu=hexagonv69 --mattr=+hvx -d - | \
+# RUN:   FileCheck %s
+# CHECK: 00000000 <.text>:
+
+{
+  V4:5.w = vadd(V1:0.w, V3:2.w)
+  vmem(r0+#0) = v4.new
+}
+# CHECK-NEXT: 1c6240c5 {  v4:5.w = vadd(v1:0.w,v3:2.w)
+# CHECK-NEXT: 2820c023    vmem(r0+#0x0) = v4.new }
+
+{
+  V4:5.w = vadd(V1:0.w, V3:2.w)
+  vmem(r0+#0) = v5.new
+}
+# CHECK-NEXT: 1c6240c5 {  v4:5.w = vadd(v1:0.w,v3:2.w)
+# CHECK-NEXT: 2820c022    vmem(r0+#0x0) = v5.new }