[ARM] Add predicated shift patterns

[dmgreen]

Summary

This uses the patterns defined in MVE_TwoOpPattern to add predicated patterns for vshls/u instructions.

[samtebbs]

LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

 }
 
 defm MVE_VSHL_by_vec   : mve_shift_by_vec_multi<"vshl",   0b0, 0b0>;
 defm MVE_VQSHL_by_vec  : mve_shift_by_vec_multi<"vqshl",  0b1, 0b0>;
 defm MVE_VQRSHL_by_vec : mve_shift_by_vec_multi<"vqrshl", 0b1, 0b1>;
 defm MVE_VRSHL_by_vec  : mve_shift_by_vec_multi<"vrshl",  0b0, 0b1>;
 
 let Predicates = [HasMVEInt] in {
-  def : Pat<(v4i32 (ARMvshlu (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn))),
-            (v4i32 (MVE_VSHL_by_vecu32 (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)))>;
-  def : Pat<(v8i16 (ARMvshlu (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn))),
-            (v8i16 (MVE_VSHL_by_vecu16 (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)))>;
-  def : Pat<(v16i8 (ARMvshlu (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
-            (v16i8 (MVE_VSHL_by_vecu8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
-
-  def : Pat<(v4i32 (ARMvshls (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn))),
-            (v4i32 (MVE_VSHL_by_vecs32 (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)))>;
-  def : Pat<(v8i16 (ARMvshls (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn))),
-            (v8i16 (MVE_VSHL_by_vecs16 (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)))>;
-  def : Pat<(v16i8 (ARMvshls (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
-            (v16i8 (MVE_VSHL_by_vecs8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
+  defm : MVE_TwoOpPattern<MVE_v16i8, ARMvshlu, int_arm_mve_vshl_vector_predicated,
+                          (? (i32 0), (i32 0), (i32 1)), MVE_VSHL_by_vecu8, null_frag>;
+  defm : MVE_TwoOpPattern<MVE_v8i16, ARMvshlu, int_arm_mve_vshl_vector_predicated,
+                          (? (i32 0), (i32 0), (i32 1)), MVE_VSHL_by_vecu16, null_frag>;
+  defm : MVE_TwoOpPattern<MVE_v4i32, ARMvshlu, int_arm_mve_vshl_vector_predicated,
+                          (? (i32 0), (i32 0), (i32 1)), MVE_VSHL_by_vecu32, null_frag>;
+  defm : MVE_TwoOpPattern<MVE_v16i8, ARMvshls, int_arm_mve_vshl_vector_predicated,
+                          (? (i32 0), (i32 0), (i32 0)), MVE_VSHL_by_vecs8, null_frag>;
+  defm : MVE_TwoOpPattern<MVE_v8i16, ARMvshls, int_arm_mve_vshl_vector_predicated,
+                          (? (i32 0), (i32 0), (i32 0)), MVE_VSHL_by_vecs16, null_frag>;
+  defm : MVE_TwoOpPattern<MVE_v4i32, ARMvshls, int_arm_mve_vshl_vector_predicated,
+                          (? (i32 0), (i32 0), (i32 0)), MVE_VSHL_by_vecs32, null_frag>;
 }
 
 class MVE_shift_with_imm<string iname, string suffix, dag oops, dag iops,
                          string ops, vpred_ops vpred, string cstr,
                          bits<2> vecsize, list<dag> pattern=[]>
   : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, vecsize, pattern> {
   bits<4> Qd;
   bits<4> Qm;

llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll

 ; CHECK-NEXT:    vpush {d8, d9, d10, d11}
 ; CHECK-NEXT:    vmovlt.u16 q2, q1
 ; CHECK-NEXT:    vmovlt.s16 q3, q0
 ; CHECK-NEXT:    vadd.i32 q4, q3, q2
 ; CHECK-NEXT:    vneg.s32 q5, q2
 ; CHECK-NEXT:    vshl.s32 q4, q4, q5
 ; CHECK-NEXT:    vneg.s32 q5, q3
 ; CHECK-NEXT:    vsub.i32 q4, q4, q2
-; CHECK-NEXT:    vcmp.i32 eq, q3, q2
 ; CHECK-NEXT:    vmul.i32 q4, q4, q2
 ; CHECK-NEXT:    vmovlb.u16 q1, q1
 ; CHECK-NEXT:    vshl.u32 q4, q4, q5
 ; CHECK-NEXT:    vmovlb.s16 q0, q0
-; CHECK-NEXT:    vshl.u32 q4, q4, q2
+; CHECK-NEXT:    vpt.i32 eq, q3, q2
+; CHECK-NEXT:    vshlt.u32 q2, q4, q2
 ; CHECK-NEXT:    vadd.i32 q3, q0, q1
-; CHECK-NEXT:    vpsel q2, q4, q2
 ; CHECK-NEXT:    vneg.s32 q4, q1
 ; CHECK-NEXT:    vshl.s32 q3, q3, q4
 ; CHECK-NEXT:    vneg.s32 q4, q0
 ; CHECK-NEXT:    vsub.i32 q3, q3, q1
-; CHECK-NEXT:    vcmp.i32 eq, q0, q1
 ; CHECK-NEXT:    vmul.i32 q3, q3, q1
 ; CHECK-NEXT:    vshl.u32 q3, q3, q4
-; CHECK-NEXT:    vshl.u32 q3, q3, q1
-; CHECK-NEXT:    vpsel q0, q3, q1
-; CHECK-NEXT:    vmovnt.i32 q0, q2
+; CHECK-NEXT:    vpt.i32 eq, q0, q1
+; CHECK-NEXT:    vshlt.u32 q1, q3, q1
+; CHECK-NEXT:    vmovnt.i32 q1, q2
+; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11}
 ; CHECK-NEXT:    bx lr
 entry:
   %sa = sext <8 x i16> %a to <8 x i32>
   %sb = zext <8 x i16> %b to <8 x i32>
   %add = add <8 x i32> %sa, %sb
   %ashr = ashr <8 x i32> %add, %sb
   %sub = sub <8 x i32> %ashr, %sb

 ; CHECK-NEXT:    vpush {d8, d9, d10, d11}
 ; CHECK-NEXT:    vmovlt.u8 q2, q1
 ; CHECK-NEXT:    vmovlt.s8 q3, q0
 ; CHECK-NEXT:    vadd.i16 q4, q3, q2
 ; CHECK-NEXT:    vneg.s16 q5, q2
 ; CHECK-NEXT:    vshl.s16 q4, q4, q5
 ; CHECK-NEXT:    vneg.s16 q5, q3
 ; CHECK-NEXT:    vsub.i16 q4, q4, q2
-; CHECK-NEXT:    vcmp.i16 eq, q3, q2
 ; CHECK-NEXT:    vmul.i16 q4, q4, q2
 ; CHECK-NEXT:    vmovlb.u8 q1, q1
 ; CHECK-NEXT:    vshl.u16 q4, q4, q5
 ; CHECK-NEXT:    vmovlb.s8 q0, q0
-; CHECK-NEXT:    vshl.u16 q4, q4, q2
+; CHECK-NEXT:    vpt.i16 eq, q3, q2
+; CHECK-NEXT:    vshlt.u16 q2, q4, q2
 ; CHECK-NEXT:    vadd.i16 q3, q0, q1
-; CHECK-NEXT:    vpsel q2, q4, q2
 ; CHECK-NEXT:    vneg.s16 q4, q1
 ; CHECK-NEXT:    vshl.s16 q3, q3, q4
 ; CHECK-NEXT:    vneg.s16 q4, q0
 ; CHECK-NEXT:    vsub.i16 q3, q3, q1
-; CHECK-NEXT:    vcmp.i16 eq, q0, q1
 ; CHECK-NEXT:    vmul.i16 q3, q3, q1
 ; CHECK-NEXT:    vshl.u16 q3, q3, q4
-; CHECK-NEXT:    vshl.u16 q3, q3, q1
-; CHECK-NEXT:    vpsel q0, q3, q1
-; CHECK-NEXT:    vmovnt.i16 q0, q2
+; CHECK-NEXT:    vpt.i16 eq, q0, q1
+; CHECK-NEXT:    vshlt.u16 q1, q3, q1
+; CHECK-NEXT:    vmovnt.i16 q1, q2
+; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11}
 ; CHECK-NEXT:    bx lr
 entry:
   %sa = sext <16 x i8> %a to <16 x i16>
   %sb = zext <16 x i8> %b to <16 x i16>
   %add = add <16 x i16> %sa, %sb
   %ashr = ashr <16 x i16> %add, %sb
   %sub = sub <16 x i16> %ashr, %sb

llvm/test/CodeGen/Thumb2/mve-pred-selectop.ll

entry:
   %a = xor <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @shl_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: shl_v4i32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u32 q1, q1, q2
-; CHECK-NEXT:    vcmp.i32 eq, q0, zr
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i32 eq, q0, zr
+; CHECK-NEXT:    vshlt.u32 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <4 x i32> %z, zeroinitializer
   %a = shl <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @shl_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {
 ; CHECK-LABEL: shl_v8i16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u16 q1, q1, q2
-; CHECK-NEXT:    vcmp.i16 eq, q0, zr
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i16 eq, q0, zr
+; CHECK-NEXT:    vshlt.u16 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <8 x i16> %z, zeroinitializer
   %a = shl <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @shl_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {
 ; CHECK-LABEL: shl_v16i8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u8 q1, q1, q2
-; CHECK-NEXT:    vcmp.i8 eq, q0, zr
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i8 eq, q0, zr
+; CHECK-NEXT:    vshlt.u8 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <16 x i8> %z, zeroinitializer
   %a = shl <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: ashr_v4i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q2, q2
-; CHECK-NEXT:    vcmp.i32 eq, q0, zr
-; CHECK-NEXT:    vshl.s32 q1, q1, q2
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i32 eq, q0, zr
+; CHECK-NEXT:    vshlt.s32 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <4 x i32> %z, zeroinitializer
   %a = ashr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {
 ; CHECK-LABEL: ashr_v8i16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q2, q2
-; CHECK-NEXT:    vcmp.i16 eq, q0, zr
-; CHECK-NEXT:    vshl.s16 q1, q1, q2
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i16 eq, q0, zr
+; CHECK-NEXT:    vshlt.s16 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <8 x i16> %z, zeroinitializer
   %a = ashr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {
 ; CHECK-LABEL: ashr_v16i8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q2, q2
-; CHECK-NEXT:    vcmp.i8 eq, q0, zr
-; CHECK-NEXT:    vshl.s8 q1, q1, q2
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i8 eq, q0, zr
+; CHECK-NEXT:    vshlt.s8 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <16 x i8> %z, zeroinitializer
   %a = ashr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: lshr_v4i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q2, q2
-; CHECK-NEXT:    vcmp.i32 eq, q0, zr
-; CHECK-NEXT:    vshl.u32 q1, q1, q2
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i32 eq, q0, zr
+; CHECK-NEXT:    vshlt.u32 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <4 x i32> %z, zeroinitializer
   %a = lshr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {
 ; CHECK-LABEL: lshr_v8i16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q2, q2
-; CHECK-NEXT:    vcmp.i16 eq, q0, zr
-; CHECK-NEXT:    vshl.u16 q1, q1, q2
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i16 eq, q0, zr
+; CHECK-NEXT:    vshlt.u16 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <8 x i16> %z, zeroinitializer
   %a = lshr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {
 ; CHECK-LABEL: lshr_v16i8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q2, q2
-; CHECK-NEXT:    vcmp.i8 eq, q0, zr
-; CHECK-NEXT:    vshl.u8 q1, q1, q2
-; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vpt.i8 eq, q0, zr
+; CHECK-NEXT:    vshlt.u8 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp eq <16 x i8> %z, zeroinitializer
   %a = lshr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z
   ret <16 x i8> %b
 }
 

llvm/test/CodeGen/Thumb2/mve-pred-selectop2.ll

entry:
   %a = xor <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: shl_v4i32_x:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u32 q1, q0, q1
 ; CHECK-NEXT:    vctp.32 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = shl <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: shl_v8i16_x:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u16 q1, q0, q1
 ; CHECK-NEXT:    vctp.16 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = shl <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: shl_v16i8_x:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u8 q1, q0, q1
 ; CHECK-NEXT:    vctp.8 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = shl <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v4i32_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q1, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.s32 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.s32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = ashr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v8i16_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q1, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.s16 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.s16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = ashr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v16i8_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q1, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.s8 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.s8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = ashr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v4i32_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q1, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.u32 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = lshr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v8i16_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q1, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.u16 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = lshr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v16i8_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q1, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.u8 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = lshr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x
   ret <16 x i8> %b
 }
 
entry:
   %a = xor <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: shl_v4i32_y:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u32 q0, q0, q1
 ; CHECK-NEXT:    vctp.32 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u32 q1, q0, q1
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = shl <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: shl_v8i16_y:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u16 q0, q0, q1
 ; CHECK-NEXT:    vctp.16 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u16 q1, q0, q1
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = shl <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: shl_v16i8_y:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u8 q0, q0, q1
 ; CHECK-NEXT:    vctp.8 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u8 q1, q0, q1
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = shl <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v4i32_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q2, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.s32 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.s32 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = ashr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v8i16_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q2, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.s16 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.s16 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = ashr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v16i8_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q2, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.s8 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.s8 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = ashr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v4i32_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q2, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.u32 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u32 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = lshr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v8i16_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q2, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.u16 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u16 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = lshr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v16i8_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q2, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.u8 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u8 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = lshr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y
   ret <16 x i8> %b
 }

llvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll

entry:
   %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer
   %b = xor <16 x i8> %a, %x
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: shl_v4i32_x:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u32 q1, q0, q1
 ; CHECK-NEXT:    vctp.32 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer
   %b = shl <4 x i32> %x, %a
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: shl_v8i16_x:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u16 q1, q0, q1
 ; CHECK-NEXT:    vctp.16 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer
   %b = shl <8 x i16> %x, %a
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: shl_v16i8_x:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u8 q1, q0, q1
 ; CHECK-NEXT:    vctp.8 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer
   %b = shl <16 x i8> %x, %a
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v4i32_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q1, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.s32 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.s32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer
   %b = ashr <4 x i32> %x, %a
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v8i16_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q1, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.s16 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.s16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer
   %b = ashr <8 x i16> %x, %a
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v16i8_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q1, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.s8 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.s8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer
   %b = ashr <16 x i8> %x, %a
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v4i32_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q1, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.u32 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer
   %b = lshr <4 x i32> %x, %a
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v8i16_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q1, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.u16 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer
   %b = lshr <8 x i16> %x, %a
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v16i8_x:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q1, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.u8 q1, q0, q1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q0, q1
+; CHECK-NEXT:    vshlt.u8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer
   %b = lshr <16 x i8> %x, %a
   ret <16 x i8> %b
 }
 
entry:
   %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer
   %b = xor <16 x i8> %a, %y
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: shl_v4i32_y:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u32 q0, q0, q1
 ; CHECK-NEXT:    vctp.32 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u32 q1, q0, q1
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = shl <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: shl_v8i16_y:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u16 q0, q0, q1
 ; CHECK-NEXT:    vctp.16 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u16 q1, q0, q1
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = shl <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: shl_v16i8_y:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshl.u8 q0, q0, q1
 ; CHECK-NEXT:    vctp.8 r0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u8 q1, q0, q1
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = shl <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v4i32_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q2, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.s32 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.s32 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = ashr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v8i16_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q2, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.s16 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.s16 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = ashr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: ashr_v16i8_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q2, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.s8 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.s8 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = ashr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y
   ret <16 x i8> %b
 }
 
 define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v4i32_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s32 q2, q1
 ; CHECK-NEXT:    vctp.32 r0
-; CHECK-NEXT:    vshl.u32 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u32 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
   %a = lshr <4 x i32> %x, %y
   %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y
   ret <4 x i32> %b
 }
 
 define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v8i16_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s16 q2, q1
 ; CHECK-NEXT:    vctp.16 r0
-; CHECK-NEXT:    vshl.u16 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u16 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
   %a = lshr <8 x i16> %x, %y
   %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y
   ret <8 x i16> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {
 ; CHECK-LABEL: lshr_v16i8_y:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vneg.s8 q2, q1
 ; CHECK-NEXT:    vctp.8 r0
-; CHECK-NEXT:    vshl.u8 q0, q0, q2
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmovt q1, q0
+; CHECK-NEXT:    vshlt.u8 q1, q0, q2
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)
   %a = lshr <16 x i8> %x, %y
   %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y
   ret <16 x i8> %b
 }