[M68k] Override `CanLowerReturn` to fix assertion with large return

[ids1024]

Summary

If it couldn't fit the return value in two registers, this caused an error during codegen. It seems this method is implemented in other backends but not here, and allows it to pass return values in memory when it isn't able to do so in registers.

Seems to fix compilation of Rust code with certain return types: https://github.com/rust-lang/rust/issues/89498

[ids1024]

git-clang-format

[myhsu]

LGTM
I also found that several crashes when building llvm-test-suite are caused by this issue, so thanks a lot!

[glaubitz]

Yes, thanks a lot for implementing this! This addresses an important issue we're seeing with the Rust compiler.

[glaubitz]

@ids1024 Can you land this change yourself? Otherwise, it would be good if @myhsu could land it for you.

llvm/lib/Target/M68k/M68kISelLowering.h

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CCID,
                                bool IsVarArg,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                const SDLoc &DL, SelectionDAG &DAG,
                                SmallVectorImpl<SDValue> &InVals) const override;
 
   SDValue LowerCall(CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;
 
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool isVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
+
   /// Lower the result values of a call into the
   /// appropriate copies out of appropriate physical registers.
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
                       SelectionDAG &DAG) const override;
 
   bool decomposeMulByConstant(LLVMContext &Context, EVT VT,

llvm/lib/Target/M68k/M68kISelLowering.cpp

SDValue M68kTargetLowering::LowerFormalArguments(
 
   return Chain;
 }
 
 //===----------------------------------------------------------------------===//
 //              Return Value Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+bool M68kTargetLowering::CanLowerReturn(
+    CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg,
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
+  return CCInfo.CheckReturn(Outs, RetCC_M68k);
+}
+
 SDValue
 M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
                                 bool IsVarArg,
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
                                 const SmallVectorImpl<SDValue> &OutVals,
                                 const SDLoc &DL, SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   M68kMachineFunctionInfo *MFI = MF.getInfo<M68kMachineFunctionInfo>();

llvm/test/CodeGen/M68k/multiple-return.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
+
+define { i32, i32, i32, i32 } @test() {
+; CHECK-LABEL: test:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %start
+; CHECK-NEXT:    move.l (4,%sp), %a0
+; CHECK-NEXT:    move.l #23, (12,%a0)
+; CHECK-NEXT:    move.l #19, (8,%a0)
+; CHECK-NEXT:    move.l #17, (4,%a0)
+; CHECK-NEXT:    move.l #13, (%a0)
+; CHECK-NEXT:    move.l %a0, %d0
+; CHECK-NEXT:    move.l (%sp), %a1
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    move.l %a1, (%sp)
+; CHECK-NEXT:    rts
+start:
+  ret { i32, i32, i32, i32 } { i32 13, i32 17, i32 19, i32 23 }
+}