AMDGPU: Implement SIRegisterInfo::getRegPressureSetScore()

[• tstellarAMD]

Summary

This tells the scheduler it is better to increase SGPR register pressure
than VGPR register pressure. This could proably be made smarter in the
future, but this simple implementation yields fairly good results for a
large database of OpenGL shaders:

6462 shaders
Totals:
SGPRS: 320808 -> 300568 (-6.31 %)
VGPRS: 189928 -> 184176 (-3.03 %)
Code Size: 7047556 -> 7069532 (0.31 %) bytes
LDS: 83 -> 83 (0.00 %) blocks
Scratch: 1025024 -> 979968 (-4.40 %) bytes per wave

[MatzeB]

Leave review to people actually knowing AMDGPU.

[arsenm]

lib/Target/AMDGPU/SIRegisterInfo.cpp

192–193

I'm not sure what this means.

Also you can move the VGPR test under the SGPR pressure set and remove the second if

[nhaehnle]

getRegPressureSetScore seems to have been removed.

[• tstellarAMD]

Rebased and address some review comments. However, register usage is now worse
with this patch.

[• tstellarAMD]

With my recent scheduler change, this patch shows improvements again, especially
with Max Waves.

16429 shaders in 3231 tests
Totals:
SGPRS: 311488 -> 308360 (-1.00 %)
VGPRS: 209002 -> 207986 (-0.49 %)
Code Size: 7183656 -> 7297532 (1.59 %) bytes
LDS: 83 -> 83 (0.00 %) blocks
Scratch: 1600512 -> 4276224 (167.18 %) bytes per wave
Max Waves: 49208 -> 50252 (2.12 %)
Wait states: 0 -> 0 (0.00 %)

[arsenm]

Why is the scratch increase so big?

[arsenm]

Is this still needed with your new scheduler passes?

[• tstellarAMD]

Not needed any more after the recent scheduling improvements.

lib/Target/AMDGPU/SIRegisterInfo.h

public:
   unsigned reservedPrivateSegmentWaveByteOffsetReg(
     const MachineFunction &MF) const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   unsigned getRegPressureSetLimit(const MachineFunction &MF,
                                   unsigned Idx) const override;
 
+  unsigned getRegPressureSetScore(const MachineFunction &MF,
+                                  unsigned PSetID) const override;
+
   bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
 
   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS) const override;
 

lib/Target/AMDGPU/SIRegisterInfo.cpp

unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
   }
 
   if (SGPRPressureSets.test(Idx))
     return SGPRLimit;
 
   return VGPRLimit;
 }
 
+unsigned SIRegisterInfo::getRegPressureSetScore(const MachineFunction &MF,
+                                                    unsigned PSetID) const {
+
+  if (SGPRPressureSets.test(PSetID)) {
+    if (VGPRPressureSets.test(PSetID)) {
+      // If a pressure set contains vgprs and sgprs then we prefer incresing
+      // its pressure over regular register classes.  This has the hightest
+      // score.
+      return 2;
+    }
+    // If this is an SGPR pressure set we prefer increasing its pressure
+    // over VGPR pressure sets.
+    return 1;
+  }
+
+  // VGPRS.
+  return 0;
+}
+
 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
   return Fn.getFrameInfo()->hasStackObjects();
 }
 
 bool
 SIRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
   return MF.getFrameInfo()->hasStackObjects();
 }