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Differential D147675

[PowerPC] Update pr61315.ll to address D146632 failure
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Authored by maryammo on Apr 5 2023, 6:58 PM.

Details

Reviewers
stefanp
Commits
rG6dbb2a717a14: [PowerPC] Update pr61315.ll to address D146632 failure
Summary

This patch is to update pr61315.ll what was needed as part of
D146632 and caused build failures.

Diff Detail

Event Timeline

maryammo created this revision.Apr 5 2023, 6:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 5 2023, 6:58 PM
Herald added subscribers: shchenz, nemanjai. · View Herald Transcript
maryammo requested review of this revision.Apr 5 2023, 6:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 5 2023, 6:58 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
maryammo added a reviewer: stefanp.Apr 5 2023, 6:58 PM
stefanp accepted this revision.Apr 5 2023, 7:17 PM

LGTM.
I'm going to approve this to unblock the bots.

This revision is now accepted and ready to land.Apr 5 2023, 7:17 PM
This revision was landed with ongoing or failed builds.Apr 5 2023, 7:25 PM
Closed by commit rG6dbb2a717a14: [PowerPC] Update pr61315.ll to address D146632 failure (authored by maryammo). · Explain Why
This revision was automatically updated to reflect the committed changes.
maryammo added a commit: rG6dbb2a717a14: [PowerPC] Update pr61315.ll to address D146632 failure.
Harbormaster completed remote builds in B223908: Diff 511253.Apr 5 2023, 8:12 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
PowerPC/
111 lines

Diff 511255

llvm/test/CodeGen/PowerPC/pr61315.ll

; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mcpu=pwr9 -mtriple=powerpc64 < %s | FileCheck %s ; RUN: -mcpu=pwr9 -mtriple=powerpc64 < %s | FileCheck %s
define dso_local <16 x i8> @ConvertExtractedMaskBitsToVect(<16 x i8> noundef %0) local_unnamed_addr #0 { define dso_local <16 x i8> @ConvertExtractedMaskBitsToVect(<16 x i8> noundef %0) local_unnamed_addr #0 {
; CHECK: .LCPI0_0: ; CHECK: .LCPI0_0:
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-LABEL: ConvertExtractedMaskBitsToVect: ; CHECK-LABEL: ConvertExtractedMaskBitsToVect:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: xxlxor v4, v4, v4
; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: addis r3, r2, .LCPI0_1@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI0_1@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI0_1@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI0_1@toc@l
; CHECK-NEXT: xxperm v4, v2, vs0 ; CHECK-NEXT: xxperm v2, v3, vs0
; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: xxland v2, v4, vs0 ; CHECK-NEXT: xxland v2, v2, vs0
; CHECK-NEXT: vcmpequb v2, v2, v3 ; CHECK-NEXT: vcmpequb v2, v2, v3
; CHECK-NEXT: xxlnor v2, v2, v2 ; CHECK-NEXT: xxlnor v2, v2, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a4 = extractelement <16 x i8> %0, i64 7 %a4 = extractelement <16 x i8> %0, i64 7
%a5 = zext i8 %a4 to i16 %a5 = zext i8 %a4 to i16
%a6 = insertelement <8 x i16> poison, i16 %a5, i64 0 %a6 = insertelement <8 x i16> poison, i16 %a5, i64 0
%a7 = bitcast <8 x i16> %a6 to <16 x i8> %a7 = bitcast <8 x i16> %a6 to <16 x i8>
%a8 = shufflevector <16 x i8> %a7, <16 x i8> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %a8 = shufflevector <16 x i8> %a7, <16 x i8> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%a9 = and <16 x i8> %a8, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128> %a9 = and <16 x i8> %a8, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>
%a10 = icmp eq <16 x i8> %a9, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128> %a10 = icmp eq <16 x i8> %a9, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>
%a11 = sext <16 x i1> %a10 to <16 x i8> %a11 = sext <16 x i1> %a10 to <16 x i8>
ret <16 x i8> %a11 ret <16 x i8> %a11
} }
define dso_local <16 x i8> @ConvertExtractedMaskBitsToVect2(<16 x i8> noundef %0) local_unnamed_addr #0 { define dso_local <16 x i8> @ConvertExtractedMaskBitsToVect2(<16 x i8> noundef %0) local_unnamed_addr #0 {
; CHECK: .LCPI1_0: ; CHECK: .LCPI1_0:
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-LABEL: ConvertExtractedMaskBitsToVect2: ; CHECK-LABEL: ConvertExtractedMaskBitsToVect2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-NEXT: xxlxor v4, v4, v4
; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l
; CHECK-NEXT: xxperm v4, v2, vs0 ; CHECK-NEXT: xxperm v2, v3, vs0
; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: xxland v2, v4, vs0 ; CHECK-NEXT: xxland v2, v2, vs0
; CHECK-NEXT: vcmpequb v2, v2, v3 ; CHECK-NEXT: vcmpequb v2, v2, v3
; CHECK-NEXT: xxlnor v2, v2, v2 ; CHECK-NEXT: xxlnor v2, v2, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a4 = extractelement <16 x i8> %0, i64 7 %a4 = extractelement <16 x i8> %0, i64 7
%a5 = zext i8 %a4 to i32 %a5 = zext i8 %a4 to i32
%a6 = insertelement <4 x i32> poison, i32 %a5, i64 0 %a6 = insertelement <4 x i32> poison, i32 %a5, i64 0
%a7 = bitcast <4 x i32> %a6 to <16 x i8> %a7 = bitcast <4 x i32> %a6 to <16 x i8>
%a8 = shufflevector <16 x i8> %a7, <16 x i8> undef, <16 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %a8 = shufflevector <16 x i8> %a7, <16 x i8> undef, <16 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%a9 = and <16 x i8> %a8, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128> %a9 = and <16 x i8> %a8, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>
%a10 = icmp eq <16 x i8> %a9, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128> %a10 = icmp eq <16 x i8> %a9, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>
%a11 = sext <16 x i1> %a10 to <16 x i8> %a11 = sext <16 x i1> %a10 to <16 x i8>
ret <16 x i8> %a11 ret <16 x i8> %a11
} }
define dso_local <16 x i8> @ConvertExtractedMaskBitsToVect3(<8 x i16> noundef %0) local_unnamed_addr #0 { define dso_local <16 x i8> @ConvertExtractedMaskBitsToVect3(<8 x i16> noundef %0) local_unnamed_addr #0 {
; CHECK: .LCPI2_0: ; CHECK: .LCPI2_0:
; CHECK-NEXT: .byte 6 # 0x6 ; CHECK-NEXT: .byte 22 # 0x16
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 6 # 0x6 ; CHECK-NEXT: .byte 22 # 0x16
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 6 # 0x6 ; CHECK-NEXT: .byte 22 # 0x16
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 6 # 0x6 ; CHECK-NEXT: .byte 22 # 0x16
; CHECK-NEXT: .byte 7 # 0x7 ; CHECK-NEXT: .byte 23 # 0x17
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 16 # 0x10 ; CHECK-NEXT: .byte 0 # 0x0
; CHECK-LABEL: ConvertExtractedMaskBitsToVect3: ; CHECK-LABEL: ConvertExtractedMaskBitsToVect3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-NEXT: xxlxor v4, v4, v4
; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: addis r3, r2, .LCPI2_1@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI2_1@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI2_1@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI2_1@toc@l
; CHECK-NEXT: xxperm v4, v2, vs0 ; CHECK-NEXT: xxperm v2, v3, vs0
; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: xxland v2, v4, vs0 ; CHECK-NEXT: xxland v2, v2, vs0
; CHECK-NEXT: vcmpequb v2, v2, v3 ; CHECK-NEXT: vcmpequb v2, v2, v3
; CHECK-NEXT: xxlnor v2, v2, v2 ; CHECK-NEXT: xxlnor v2, v2, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a4 = extractelement <8 x i16> %0, i64 3 %a4 = extractelement <8 x i16> %0, i64 3
%a5 = zext i16 %a4 to i32 %a5 = zext i16 %a4 to i32
%a6 = insertelement <4 x i32> poison, i32 %a5, i64 0 %a6 = insertelement <4 x i32> poison, i32 %a5, i64 0
%a7 = bitcast <4 x i32> %a6 to <16 x i8> %a7 = bitcast <4 x i32> %a6 to <16 x i8>
%a8 = shufflevector <16 x i8> %a7, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %a8 = shufflevector <16 x i8> %a7, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%a9 = and <16 x i8> %a8, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128> %a9 = and <16 x i8> %a8, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>
%a10 = icmp eq <16 x i8> %a9, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128> %a10 = icmp eq <16 x i8> %a9, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>
%a11 = sext <16 x i1> %a10 to <16 x i8> %a11 = sext <16 x i1> %a10 to <16 x i8>
ret <16 x i8> %a11 ret <16 x i8> %a11
} }