[clang-format] Handle enum in Verilog
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Authored by sstwcw on Mar 31 2023, 7:33 AM.

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rymiel
HazardyKnusperkeks
owenpan
MyDeveloperDay

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rG92b2be39656b: [clang-format] Handle enum in Verilog

Summary

Verilog has enum just like C.

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Repository: rG LLVM Github Monorepo

Event Timeline

sstwcw created this revision.Mar 31 2023, 7:33 AM

Herald added projects: Restricted Project, Restricted Project, Restricted Project. · View Herald TranscriptMar 31 2023, 7:33 AM

Herald added reviewers: rymiel, HazardyKnusperkeks, owenpan, MyDeveloperDay. · View Herald Transcript

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sstwcw requested review of this revision.Mar 31 2023, 7:33 AM

Harbormaster completed remote builds in B223010: Diff 510031.Mar 31 2023, 10:21 AM

HazardyKnusperkeks accepted this revision.Mar 31 2023, 1:05 PM

This revision is now accepted and ready to land.Mar 31 2023, 1:05 PM

owenpan accepted this revision.Mar 31 2023, 5:38 PM

owenpan added inline comments.

clang/lib/Format/UnwrappedLineParser.cpp
1712–1713

MyDeveloperDay accepted this revision.Apr 1 2023, 8:15 AM

This revision was landed with ongoing or failed builds.Apr 1 2023, 10:15 AM

Closed by commit rG92b2be39656b: [clang-format] Handle enum in Verilog (authored by sstwcw). · Explain Why

This revision was automatically updated to reflect the committed changes.

sstwcw added a commit: rG92b2be39656b: [clang-format] Handle enum in Verilog.

Revision Contents
Changeset List

Path

Size

clang/

lib/

Format/

UnwrappedLineParser.cpp

14 lines

unittests/

Format/

FormatTestVerilog.cpp

14 lines

Diff 510248

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clang/lib/Format/UnwrappedLineParser.cpp