[ARM] Handle generating SEH unwind info for t2STR_PRE/t2LDR_POST

[efriedma]

Can you stick the testcase into wineh-opcodes.ll?

I'm assuming the load/store ops are getting generated by expanding a PUSH/POP, and not some other transform? (So the offset will actually reliably be 4, in practice?)

Otherwise LGTM.

[mstorsjo]

In D147212#4234136, @efriedma wrote:

Can you stick the testcase into wineh-opcodes.ll?

Oh, right - sure.

I'm assuming the load/store ops are getting generated by expanding a PUSH/POP, and not some other transform? (So the offset will actually reliably be 4, in practice?)

Not sure actually - if looking at the output of -print-after-all here, the t2STR_PRE appears as such directly, not as a transformation of something else - I don't directly see where it comes from (other than printf instrumenting the code in Target/ARM to see which reference to t2STR_PRE gets hit).

[efriedma]

In D147212#4234854, @mstorsjo wrote:

I'm assuming the load/store ops are getting generated by expanding a PUSH/POP, and not some other transform? (So the offset will actually reliably be 4, in practice?)

Not sure actually - if looking at the output of -print-after-all here, the t2STR_PRE appears as such directly, not as a transformation of something else - I don't directly see where it comes from (other than printf instrumenting the code in Target/ARM to see which reference to t2STR_PRE gets hit).

Skimming the code, it looks like it's coming out of ARMFrameLowering::emitPushInst... which should be safe in that respect.

[mstorsjo]

In D147212#4234863, @efriedma wrote:

In D147212#4234854, @mstorsjo wrote:

I'm assuming the load/store ops are getting generated by expanding a PUSH/POP, and not some other transform? (So the offset will actually reliably be 4, in practice?)

Not sure actually - if looking at the output of -print-after-all here, the t2STR_PRE appears as such directly, not as a transformation of something else - I don't directly see where it comes from (other than printf instrumenting the code in Target/ARM to see which reference to t2STR_PRE gets hit).

Skimming the code, it looks like it's coming out of ARMFrameLowering::emitPushInst... which should be safe in that respect.

Oh, indeed. Thanks for looking into it!

llvm/lib/Target/ARM/ARMFrameLowering.cpp

MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
               .addImm(/*Wide=*/1)
               .setMIFlags(Flags);
     MBB->insertAfter(MBBI, MIB);
     MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
               .addImm(/*Wide=*/1)
               .setMIFlags(Flags);
     break;
 
+  case ARM::t2STR_PRE:
+    if (MBBI->getOperand(0).getReg() == ARM::SP &&
+        MBBI->getOperand(2).getReg() == ARM::SP &&
+        MBBI->getOperand(3).getImm() == -4) {
+      unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
+      MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
+                .addImm(1 << Reg)
+                .addImm(/*Wide=*/1)
+                .setMIFlags(Flags);
+    } else {
+      report_fatal_error("No matching SEH Opcode for t2STR_PRE");
+    }
+    break;
+
+  case ARM::t2LDR_POST:
+    if (MBBI->getOperand(1).getReg() == ARM::SP &&
+        MBBI->getOperand(2).getReg() == ARM::SP &&
+        MBBI->getOperand(3).getImm() == 4) {
+      unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
+      MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
+                .addImm(1 << Reg)
+                .addImm(/*Wide=*/1)
+                .setMIFlags(Flags);
+    } else {
+      report_fatal_error("No matching SEH Opcode for t2LDR_POST");
+    }
+    break;
+
   case ARM::t2LDMIA_RET:
   case ARM::t2LDMIA_UPD:
   case ARM::t2STMDB_UPD: {
     unsigned Mask = 0;
     bool Wide = false;
     for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
       const MachineOperand &MO = MBBI->getOperand(i);
       if (!MO.isReg() || MO.isImplicit())

llvm/test/CodeGen/ARM/Windows/wineh-save-single-reg.ll

+;; Check that this produces the expected assembly output
+; RUN: llc -mtriple=thumbv7-windows -o - %s -verify-machineinstrs | FileCheck %s
+;; Also try to write an object file, which verifies that the SEH opcodes
+;; match the actual prologue/epilogue length.
+; RUN: llc -mtriple=thumbv7-windows -filetype=obj -o %t.obj %s -verify-machineinstrs
+
+; CHECK-LABEL: _Z4funcv:
+; CHECK-NEXT: .seh_proc _Z4funcv
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         str     r11, [sp, #-4]!
+; CHECK-NEXT:         .seh_save_regs_w        {r11}
+; CHECK-NEXT:         mov     r11, sp
+; CHECK-NEXT:         .seh_save_sp    r11
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK-NEXT:         mov     r0, r11
+
+; CHECK-NEXT:         .seh_startepilogue
+; CHECK-NEXT:         ldr     r11, [sp], #4
+; CHECK-NEXT:         .seh_save_regs_w        {r11}
+; CHECK-NEXT:         bx      lr
+; CHECK-NEXT:         .seh_nop
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define i32 @_Z4funcv() {
+entry:
+  %0 = tail call ptr @llvm.frameaddress.p0(i32 0)
+  %1 = ptrtoint ptr %0 to i32
+  ret i32 %1
+}
+
+declare ptr @llvm.frameaddress.p0(i32 immarg) #1