[ARM] Fold fadd of vcmul into vcmla

[dmgreen]

Summary

This adds an extra tablegen combine for folding fadd(a, vcmul(b, c)) into vcmla(a, b, c), so long as the fadd is allowed to contract.

[samtebbs]

LGTM

llvm/lib/Target/ARM/ARMInstrInfo.td

def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
   return hasNoVMLxHazardUse(N);
 }]>;
 
 // An 'fsub' node which checks for single non-hazardous use.
 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
   return hasNoVMLxHazardUse(N);
 }]>;
 
+// An 'fadd' node which can be contracted into a fma
+def fadd_contract : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
+  return N->getFlags().hasAllowContract();
+}]>;
+
 def imm_even : ImmLeaf<i32, [{ return (Imm & 1) == 0; }]>;
 def imm_odd : ImmLeaf<i32, [{ return (Imm & 1) == 1; }]>;
 
 def asr_imm : ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }], asr_imm_XFORM>;
 
 //===----------------------------------------------------------------------===//
 // NEON/MVE pattern fragments
 //

llvm/lib/Target/ARM/ARMInstrMVE.td

multiclass MVE_VCMLA_m<MVEVectorVTInfo VTI> {
   let Predicates = [HasMVEFloat] in {
     def : Pat<(VTI.Vec (int_arm_mve_vcmlaq
                             imm:$rot, (VTI.Vec MQPR:$Qd_src),
                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
               (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
                              (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                              imm:$rot))>;
 
+    def: Pat<(VTI.Vec (fadd_contract MQPR:$Qd_src,
+                            (int_arm_mve_vcmulq imm:$rot,
+                              (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm)))),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
+                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
+                             imm:$rot))>;
+
     def : Pat<(VTI.Vec (int_arm_mve_vcmlaq_predicated
                             imm:$rot, (VTI.Vec MQPR:$Qd_src),
                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                             (VTI.Pred VCCR:$mask))),
               (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qn),
                              (VTI.Vec MQPR:$Qm), imm:$rot,
                              ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
-
   }
 }
 
 defm MVE_VCMLAf16 : MVE_VCMLA_m<MVE_v8f16>;
 defm MVE_VCMLAf32 : MVE_VCMLA_m<MVE_v4f32>;
 
 class MVE_VADDSUBFMA_fp<string iname, string suffix, bits<2> size, bit bit_4,
                         bit bit_8, bit bit_21, dag iops=(ins),

llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll

entry:
   %interleaved.vec = shufflevector <2 x float> %11, <2 x float> %8, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
   ret <4 x float> %interleaved.vec
 }
 
 ; Expected to transform
 define <4 x float> @mul_addequal(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
 ; CHECK-LABEL: mul_addequal:
 ; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    add.w r12, sp, #16
 ; CHECK-NEXT:    vmov d0, r0, r1
 ; CHECK-NEXT:    mov r0, sp
-; CHECK-NEXT:    add r1, sp, #16
+; CHECK-NEXT:    vldrw.u32 q2, [r12]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0]
 ; CHECK-NEXT:    vmov d1, r2, r3
-; CHECK-NEXT:    vldrw.u32 q2, [r1]
-; CHECK-NEXT:    vcmul.f32 q3, q0, q1, #0
-; CHECK-NEXT:    vadd.f32 q2, q3, q2
+; CHECK-NEXT:    vcmla.f32 q2, q0, q1, #0
 ; CHECK-NEXT:    vcmla.f32 q2, q0, q1, #90
 ; CHECK-NEXT:    vmov r0, r1, d4
 ; CHECK-NEXT:    vmov r2, r3, d5
 ; CHECK-NEXT:    bx lr
 entry:
   %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %a.imag = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %b.real = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>

llvm/test/CodeGen/Thumb2/mve-vcmla.ll

entry:
   ret <4 x float> %res
 }
 
 
 
 define arm_aapcs_vfpcc <4 x float> @muladd_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
 ; CHECK-LABEL: muladd_f32x4:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vcmul.f32 q3, q1, q2, #0
-; CHECK-NEXT:    vadd.f32 q0, q3, q0
+; CHECK-NEXT:    vcmla.f32 q0, q1, q2, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %d = tail call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %b, <4 x float> %c)
   %res = fadd fast <4 x float> %d, %a
   ret <4 x float> %res
 }
 
 define arm_aapcs_vfpcc <4 x float> @muladd_c_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
 ; CHECK-LABEL: muladd_c_f32x4:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vcmul.f32 q3, q1, q2, #90
-; CHECK-NEXT:    vadd.f32 q0, q0, q3
+; CHECK-NEXT:    vcmla.f32 q0, q1, q2, #90
 ; CHECK-NEXT:    bx lr
 entry:
   %d = tail call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %b, <4 x float> %c)
   %res = fadd fast <4 x float> %a, %d
   ret <4 x float> %res
 }
 
 define arm_aapcs_vfpcc <8 x half> @muladd_f16x4(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
 ; CHECK-LABEL: muladd_f16x4:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vcmul.f16 q1, q1, q2, #180
-; CHECK-NEXT:    vadd.f16 q0, q1, q0
+; CHECK-NEXT:    vcmla.f16 q0, q1, q2, #180
 ; CHECK-NEXT:    bx lr
 entry:
   %d = tail call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %b, <8 x half> %c)
   %res = fadd fast <8 x half> %d, %a
   ret <8 x half> %res
 }
 
 define arm_aapcs_vfpcc <8 x half> @muladd_c_f16x4(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
 ; CHECK-LABEL: muladd_c_f16x4:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vcmul.f16 q1, q1, q2, #270
-; CHECK-NEXT:    vadd.f16 q0, q0, q1
+; CHECK-NEXT:    vcmla.f16 q0, q1, q2, #270
 ; CHECK-NEXT:    bx lr
 entry:
   %d = tail call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %b, <8 x half> %c)
   %res = fadd fast <8 x half> %a, %d
   ret <8 x half> %res
 }
 
 define arm_aapcs_vfpcc <4 x float> @muladd_nonfast_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {