[X86] Preserve !pcsections on atomic intrinsics

[melver]

Summary

Preserve !pcsections metadata on X86-only atomic intrinsics when
expanding higher-level atomics.

llvm/lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::shouldExpandLogicAtomicRMWInIR(AtomicRMWInst *AI) const {
   // If atomic XOR/OR need to be setting and testing the same bit.
   return (BitChange.second == ShiftBit && BitTested.second == ShiftBit)
              ? AtomicExpansionKind::BitTestIntrinsic
              : AtomicExpansionKind::CmpXChg;
 }
 
 void X86TargetLowering::emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const {
   IRBuilder<> Builder(AI);
+  Builder.CollectMetadataToCopy(AI, {LLVMContext::MD_pcsections});
   Intrinsic::ID IID_C = Intrinsic::not_intrinsic;
   Intrinsic::ID IID_I = Intrinsic::not_intrinsic;
   switch (AI->getOperation()) {
   default:
     llvm_unreachable("Unknown atomic operation");
   case AtomicRMWInst::Or:
     IID_C = Intrinsic::x86_atomic_bts;
     IID_I = Intrinsic::x86_atomic_bts_rm;
static bool shouldExpandCmpArithRMWInIR(AtomicRMWInst *AI) {
   }
 
   return false;
 }
 
 void X86TargetLowering::emitCmpArithAtomicRMWIntrinsic(
     AtomicRMWInst *AI) const {
   IRBuilder<> Builder(AI);
+  Builder.CollectMetadataToCopy(AI, {LLVMContext::MD_pcsections});
   Instruction *TempI = nullptr;
   LLVMContext &Ctx = AI->getContext();
   ICmpInst *ICI = dyn_cast<ICmpInst>(AI->user_back());
   if (!ICI) {
     TempI = AI->user_back();
     assert(TempI->hasOneUse() && "Must have one use");
     ICI = cast<ICmpInst>(TempI->user_back());
   }
X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
   // lowering available in lowerAtomicArith.
   // TODO: push more cases through this path.
   if (auto *C = dyn_cast<ConstantInt>(AI->getValOperand()))
     if (AI->getOperation() == AtomicRMWInst::Or && C->isZero() &&
         AI->use_empty())
       return nullptr;
 
   IRBuilder<> Builder(AI);
+  Builder.CollectMetadataToCopy(AI, {LLVMContext::MD_pcsections});
   Module *M = Builder.GetInsertBlock()->getParent()->getParent();
   auto SSID = AI->getSyncScopeID();
   // We must restrict the ordering to avoid generating loads with Release or
   // ReleaseAcquire orderings.
   auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
 
   // Before the load we need a fence. Here is an example lifted from
   // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence

llvm/test/CodeGen/X86/pcsections-atomics.ll

 ; O3-NEXT:    retq
 entry:
   load volatile i64, ptr @foo, align 8
   %x = cmpxchg ptr %a, ptr %v1, ptr %v2 seq_cst seq_cst, align 8, !pcsections !0
   store volatile i64 1, ptr @foo, align 8
   ret void
 }
 
+define i64 @atomic_use_cond(ptr %a) {
+; O0-LABEL: atomic_use_cond:
+; O0:       # %bb.0: # %entry
+; O0-NEXT:  .Lpcsection412:
+; O0-NEXT:    lock decq (%rdi)
+; O0-NEXT:  .Lpcsection413:
+; O0-NEXT:    sete %al
+; O0-NEXT:    testb $1, %al
+; O0-NEXT:    je .LBB197_2
+; O0-NEXT:  # %bb.1: # %then
+; O0-NEXT:    movl $1, %eax
+; O0-NEXT:    retq
+; O0-NEXT:  .LBB197_2: # %else
+; O0-NEXT:    movl $2, %eax
+; O0-NEXT:    retq
+;
+; O1-LABEL: atomic_use_cond:
+; O1:       # %bb.0: # %entry
+; O1-NEXT:  .Lpcsection327:
+; O1-NEXT:    lock decq (%rdi)
+; O1-NEXT:    jne .LBB197_2
+; O1-NEXT:  # %bb.1: # %then
+; O1-NEXT:    movl $1, %eax
+; O1-NEXT:    retq
+; O1-NEXT:  .LBB197_2: # %else
+; O1-NEXT:    movl $2, %eax
+; O1-NEXT:    retq
+;
+; O2-LABEL: atomic_use_cond:
+; O2:       # %bb.0: # %entry
+; O2-NEXT:  .Lpcsection327:
+; O2-NEXT:    lock decq (%rdi)
+; O2-NEXT:    jne .LBB197_2
+; O2-NEXT:  # %bb.1: # %then
+; O2-NEXT:    movl $1, %eax
+; O2-NEXT:    retq
+; O2-NEXT:  .LBB197_2: # %else
+; O2-NEXT:    movl $2, %eax
+; O2-NEXT:    retq
+;
+; O3-LABEL: atomic_use_cond:
+; O3:       # %bb.0: # %entry
+; O3-NEXT:  .Lpcsection327:
+; O3-NEXT:    lock decq (%rdi)
+; O3-NEXT:    jne .LBB197_2
+; O3-NEXT:  # %bb.1: # %then
+; O3-NEXT:    movl $1, %eax
+; O3-NEXT:    retq
+; O3-NEXT:  .LBB197_2: # %else
+; O3-NEXT:    movl $2, %eax
+; O3-NEXT:    retq
+entry:
+  %x = atomicrmw sub ptr %a, i64 1 seq_cst, align 8, !pcsections !0
+  %y = icmp eq i64 %x, 1
+  br i1 %y, label %then, label %else
+
+then:
+  ret i64 1
+
+else:
+  ret i64 2
+}
+
 !0 = !{!"somesection"}