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Differential D14605

[mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions
ClosedPublic

Authored by zbuljan on Nov 12 2015, 1:53 AM.

Details

Reviewers
dsanders
zoran.jovanovic
hvarga
Commits
rL254291: [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W…
Summary

The patch implements microMIPSDSP instructions: PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 40018.Nov 12 2015, 1:53 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptNov 12 2015, 1:53 AM
zbuljan updated this revision to Diff 40392.Nov 17 2015, 5:58 AM

Rebased to work with top of the tree. microMIPSDSPr1 assembler and disassembler tests added to microMIPSDSPr2 test files.

dsanders accepted this revision.Nov 27 2015, 1:49 AM
dsanders edited edge metadata.

LGTM

This revision is now accepted and ready to land.Nov 27 2015, 1:49 AM
Closed by commit rL254291: [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W… (authored by zbuljan). · Explain WhyNov 30 2015, 12:40 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
12 lines
20 lines
16 lines
test/
MC/
Disassembler/
Mips/
micromips-dsp/
4 lines
micromips-dspr2/
7 lines
Mips/
micromips-dsp/
4 lines
micromips-dspr2/
7 lines

Diff 40392

lib/Target/Mips/MicroMipsDSPInstrFormats.td

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Linesclass POOL32A_1RIMM5AC_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
let Inst{31-26} = 0b000000; let Inst{31-26} = 0b000000;
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = imm; let Inst{20-16} = imm;
let Inst{15-14} = ac; let Inst{15-14} = ac;
let Inst{13-6} = funct; let Inst{13-6} = funct;
let Inst{5-0} = 0b111100; let Inst{5-0} = 0b111100;
} }
class POOL32A_2RSA5_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
bits<5> rt;
bits<5> rs;
bits<5> sa;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-11} = sa;
let Inst{10-0} = op;
}

lib/Target/Mips/MicroMipsDSPInstrInfo.td

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class EXTR_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr.w", 0b00111001>; class EXTR_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr.w", 0b00111001>;
class EXTR_R_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_r.w", 0b01111001>; class EXTR_R_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_r.w", 0b01111001>;
class EXTR_RS_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_rs.w", 0b10111001>; class EXTR_RS_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_rs.w", 0b10111001>;
class EXTR_S_H_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_s.h", 0b11111001>; class EXTR_S_H_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_s.h", 0b11111001>;
class EXTRV_W_MM_ENC : POOL32A_2RAC_FMT<"extrv.w", 0b00111010>; class EXTRV_W_MM_ENC : POOL32A_2RAC_FMT<"extrv.w", 0b00111010>;
class EXTRV_R_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_r.w", 0b01111010>; class EXTRV_R_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_r.w", 0b01111010>;
class EXTRV_RS_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_rs.w", 0b10111010>; class EXTRV_RS_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_rs.w", 0b10111010>;
class EXTRV_S_H_MM_ENC : POOL32A_2RAC_FMT<"extrv_s.h", 0b11111010>; class EXTRV_S_H_MM_ENC : POOL32A_2RAC_FMT<"extrv_s.h", 0b11111010>;
class PRECR_QB_PH_MMR2_ENC : POOL32A_3RB0_FMT<"precr.qb.ph", 0b0001101101>;
class PRECR_SRA_PH_W_MMR2_ENC
: POOL32A_2RSA5_FMT<"precr_sra.ph.w", 0b01111001101>;
class PRECR_SRA_R_PH_W_MMR2_ENC
: POOL32A_2RSA5_FMT<"precr_sra_r.ph.w", 0b11111001101>;
class PRECRQ_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq.ph.w", 0b0011101101>;
class PRECRQ_QB_PH_MM_ENC : POOL32A_3RB0_FMT<"precrq.qb.ph", 0b0010101101>;
class PRECRQU_S_QB_PH_MM_ENC
: POOL32A_3RB0_FMT<"precrqu_s.qb.ph", 0b0101101101>;
class PRECRQ_RS_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq_rs.ph.w", 0b0100101101>;
// Instruction desc. // Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode, class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand ROD, InstrItinClass itin, RegisterOperand ROD,
RegisterOperand ROS = ROD> { RegisterOperand ROS = ROD> {
dag OutOperandList = (outs ROD:$rt); dag OutOperandList = (outs ROD:$rt);
dag InOperandList = (ins ROS:$rs); dag InOperandList = (ins ROS:$rs);
string AsmString = !strconcat(opstr, "\t$rt, $rs"); string AsmString = !strconcat(opstr, "\t$rt, $rs");
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def EXTR_W_MM : DspMMRel, EXTR_W_MM_ENC, EXTR_W_MM_DESC; def EXTR_W_MM : DspMMRel, EXTR_W_MM_ENC, EXTR_W_MM_DESC;
def EXTR_R_W_MM : DspMMRel, EXTR_R_W_MM_ENC, EXTR_R_W_MM_DESC; def EXTR_R_W_MM : DspMMRel, EXTR_R_W_MM_ENC, EXTR_R_W_MM_DESC;
def EXTR_RS_W_MM : DspMMRel, EXTR_RS_W_MM_ENC, EXTR_RS_W_MM_DESC; def EXTR_RS_W_MM : DspMMRel, EXTR_RS_W_MM_ENC, EXTR_RS_W_MM_DESC;
def EXTR_S_H_MM : DspMMRel, EXTR_S_H_MM_ENC, EXTR_S_H_MM_DESC; def EXTR_S_H_MM : DspMMRel, EXTR_S_H_MM_ENC, EXTR_S_H_MM_DESC;
def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC; def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC;
def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC; def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC;
def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC; def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC;
def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC; def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC;
def PRECRQ_PH_W_MM : DspMMRel, PRECRQ_PH_W_MM_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_QB_PH_MM : DspMMRel, PRECRQ_QB_PH_MM_ENC, PRECRQ_QB_PH_DESC;
def PRECRQU_S_QB_PH_MM : DspMMRel, PRECRQU_S_QB_PH_MM_ENC, PRECRQU_S_QB_PH_DESC;
def PRECRQ_RS_PH_W_MM : DspMMRel, PRECRQ_RS_PH_W_MM_ENC, PRECRQ_RS_PH_W_DESC;
// microMIPS DSP Rev 2 // microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2; ISA_DSPR2;
def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2; def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2; def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2; def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2; def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
Show All 17 Lines
def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2; def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2;
def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2; def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2; def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2;
def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2; def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2; def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2;
def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2; def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2; def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2;
def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2; def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
def PRECR_QB_PH_MMR2 : DspMMRel, PRECR_QB_PH_MMR2_ENC, PRECR_QB_PH_DESC,
ISA_DSPR2;
def PRECR_SRA_PH_W_MMR2 : DspMMRel, PRECR_SRA_PH_W_MMR2_ENC,
PRECR_SRA_PH_W_DESC, ISA_DSPR2;
def PRECR_SRA_R_PH_W_MMR2 : DspMMRel, PRECR_SRA_R_PH_W_MMR2_ENC,
PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;

lib/Target/Mips/MipsDSPInstrInfo.td

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class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand ROD, InstrItinClass itin, RegisterOperand ROD,
RegisterOperand ROS, RegisterOperand ROT = ROS> { RegisterOperand ROS, RegisterOperand ROT = ROS> {
dag OutOperandList = (outs ROD:$rd); dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROS:$rs, ROT:$rt); dag InOperandList = (ins ROS:$rs, ROT:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
InstrItinClass Itinerary = itin; InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
} }
class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand ROT, InstrItinClass itin, RegisterOperand ROT,
RegisterOperand ROS = ROT> { RegisterOperand ROS = ROT> {
dag OutOperandList = (outs ROT:$rt); dag OutOperandList = (outs ROT:$rt);
dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src); dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))]; list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
InstrItinClass Itinerary = itin; InstrItinClass Itinerary = itin;
string Constraints = "$src = $rt"; string Constraints = "$src = $rt";
string BaseOpcode = instr_asm;
} }
class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand ROD, InstrItinClass itin, RegisterOperand ROD,
RegisterOperand ROT = ROD> { RegisterOperand ROT = ROD> {
dag OutOperandList = (outs ROD:$rd); dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROT:$rt); dag InOperandList = (ins ROT:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
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def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC; def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC; def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC; def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC; def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
def MODSUB : MODSUB_ENC, MODSUB_DESC; def MODSUB : MODSUB_ENC, MODSUB_DESC;
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC; def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
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def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC; def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC; def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC; def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC; def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC; def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC; def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC; def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
def APPEND : APPEND_ENC, APPEND_DESC; def APPEND : APPEND_ENC, APPEND_DESC;
def BALIGN : BALIGN_ENC, BALIGN_DESC; def BALIGN : BALIGN_ENC, BALIGN_DESC;
▲ Show 20 Lines • Show All 181 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips-dsp/valid.txt

Show All 36 Lines
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6 0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8 0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10 0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12 0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14 0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16 0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18 0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20 0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x01 0x49 0x40 0xed # CHECK: precrq.ph.w $8, $9, $10
0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5 0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5
0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5 0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5
0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5 0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5 0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
Show All 13 Lines

test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6 0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8 0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10 0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12 0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14 0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16 0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18 0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20 0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x00 0x62 0x08 0x6d # CHECK: precr.qb.ph $1, $2, $3
0x00 0x85 0x0b 0xcd # CHECK: precr_sra.ph.w $4, $5, 1
0x00 0xc7 0x17 0xcd # CHECK: precr_sra_r.ph.w $6, $7, 2
0x01 0x49 0x40 0xed # CHECK: precrq.ph.w $8, $9, $10
0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5 0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5
0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5 0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5
0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5 0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5 0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
Show All 27 Lines

test/MC/Mips/micromips-dsp/valid.s

Show All 37 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c] precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c] precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c] precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c] precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c] preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c] preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c] preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c] preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
precrq.ph.w $8, $9, $10 # CHECK: precrq.ph.w $8, $9, $10 # encoding: [0x01,0x49,0x40,0xed]
precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad]
precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5] shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5] shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c] shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e] shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e]
shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e] shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e]
shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95] shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5] shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5]
shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5] shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5]
Show All 13 Lines

test/MC/Mips/micromips-dspr2/valid.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c] precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c] precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c] precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c] precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c] preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c] preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c] preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c] preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
precr.qb.ph $1, $2, $3 # CHECK: precr.qb.ph $1, $2, $3 # encoding: [0x00,0x62,0x08,0x6d]
precr_sra.ph.w $4, $5, 1 # CHECK: precr_sra.ph.w $4, $5, 1 # encoding: [0x00,0x85,0x0b,0xcd]
precr_sra_r.ph.w $6, $7, 2 # CHECK: precr_sra_r.ph.w $6, $7, 2 # encoding: [0x00,0xc7,0x17,0xcd]
precrq.ph.w $8, $9, $10 # CHECK: precrq.ph.w $8, $9, $10 # encoding: [0x01,0x49,0x40,0xed]
precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad]
precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5] shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5] shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c] shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e] shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e]
shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e] shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e]
shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95] shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5] shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5]
shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5] shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5]
Show All 27 Lines