[AArchExpandPseudo] Preserve instruction debug number in expansions

[fdeazeve]

Summary

This is an initial attempt at preserving debug information in the pseudo
instruction expansion of the AArch backend. In particular, we preserve
the instruction number required by the InstrRef implementation of live
debug values.

There are many other expansions that need to be considered, but the ones
addressed in this commit should be extremely common, as they handle most
arithmetic and logical instructions.

[jmorse]

LGTM, assuming that the instructions affected always have the same signature / format. (I know very little aarch64).

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

case AArch64::ORRXrr: {
     MBB.insert(MBBI, NewMI);
     MachineInstrBuilder MIB1(MF, NewMI);
     MIB1->setPCSections(MF, MI.getPCSections());
     MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define)
         .add(MI.getOperand(1))
         .add(MI.getOperand(2))
         .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
     transferImpOps(MI, MIB1, MIB1);
+    if (auto DebugNumber = MI.peekDebugInstrNum())
+      NewMI->setDebugInstrNum(DebugNumber);
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::LOADgot: {
     MachineFunction *MF = MBB.getParent();
     Register DstReg = MI.getOperand(0).getReg();
     const MachineOperand &MO1 = MI.getOperand(1);

llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir

 # RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
 
 ---
 # CHECK-LABEL:  name: test
 # CHECK-LABEL:  bb.0:
-# CHECK:          $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv
-# CHECK-NEXT:     $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv
+# CHECK:          $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv, debug-instr-number 1
+# CHECK-NEXT:     $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv, debug-instr-number 2
 # CHECK-NEXT:     RET undef $lr
 #
 name:            test
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w5, $w6, $x2, $x3
 
-    renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv
-    renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv
+    renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv, debug-instr-number 1
+    renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv, debug-instr-number 2
     RET_ReallyLR
 
 ...