[PowerPC] remove side effect for some cases for saturate instructions

[shchenz]

Summary

Fixes https://github.com/llvm/llvm-project/issues/60684

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15790–15822

Can you please do the following two things:

1. Add a comment explaining that these sum-across intrinsics only have a chain due to the side effects. If we know that the SAT bit will not be set, we can replace any uses of their chain with the input chain.
2. Combine these into a single switch - along the lines of:

switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
case Intrinsic::ppc_vsx_lxvw4x:
case Intrinsic::ppc_vsx_lxvd2x:
  if (Subtarget.needsSwapsForVSXMemOps())
    return expandVSXLoadForLE(N, DCI);
  break;
case Intrinsic::ppc_altivec_vsum4sbs:
case Intrinsic::ppc_altivec_vsum4shs:
case Intrinsic::ppc_altivec_vsum4ubs: {
  // handle the chain replacement
}
}

[shchenz]

address @nemanjai comments

[shchenz]

gentle ping @nemanjai . Do you have further comments? Thank you!

[nemanjai]

LGTM. I don't think that the test improvement requires another review.

llvm/test/CodeGen/PowerPC/vector-sum-sat-bit-side-effect.ll

12

I think it would be more useful to add a use of the actual sum in at least one of the tests. The test would have one call that is used and one that is unused. Previous to this patch, we would emit both and with this patch, we only emit the one that is used.

[shchenz]

llvm/test/CodeGen/PowerPC/vector-sum-sat-bit-side-effect.ll

12

Sure, I will add 3 new cases in the commit. And these cases will contains two calls, one call has user and one call has no user, so this call can be optimized by this patch.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case ISD::INTRINSIC_WO_CHAIN: {
             return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1);
           }
         }
       }
     }
 
     break;
   case ISD::INTRINSIC_W_CHAIN:
-    // For little endian, VSX loads require generating lxvd2x/xxswapd.
-    // Not needed on ISA 3.0 based CPUs since we have a non-permuting load.
-    if (Subtarget.needsSwapsForVSXMemOps()) {
-      switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
-      default:
-        break;
-      case Intrinsic::ppc_vsx_lxvw4x:
-      case Intrinsic::ppc_vsx_lxvd2x:
+    case Intrinsic::ppc_altivec_vsum4sbs:
+    case Intrinsic::ppc_altivec_vsum4shs:
+    case Intrinsic::ppc_altivec_vsum4ubs: {
+      // These sum-across intrinsics only have a chain due to the side effect
+      // that they may set the SAT bit. If we know the SAT bit will not be set
+      // for some inputs, we can replace any uses of their chain with the input
+      // chain.
+      if (BuildVectorSDNode *BVN =
+              dyn_cast<BuildVectorSDNode>(N->getOperand(3))) {
+        APInt APSplatBits, APSplatUndef;
+        unsigned SplatBitSize;
+        bool HasAnyUndefs;
+        bool BVNIsConstantSplat = BVN->isConstantSplat(
+            APSplatBits, APSplatUndef, SplatBitSize, HasAnyUndefs, 0,
+            !Subtarget.isLittleEndian());
+        // If the constant splat vector is 0, the SAT bit will not be set.
+        if (BVNIsConstantSplat && APSplatBits == 0)
+          DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), N->getOperand(0));
+      }
+      return SDValue();
+    }
+      // For little endian, VSX loads require generating lxvd2x/xxswapd.
+      // Not needed on ISA 3.0 based CPUs since we have a non-permuting load.
+      if (Subtarget.needsSwapsForVSXMemOps())
         return expandVSXLoadForLE(N, DCI);
-      }
+      break;
     }
     break;
   case ISD::INTRINSIC_VOID:
     // For little endian, VSX stores require generating xxswapd/stxvd2x.
     // Not needed on ISA 3.0 based CPUs since we have a non-permuting store.
     if (Subtarget.needsSwapsForVSXMemOps()) {
       switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
       default:
         break;
       case Intrinsic::ppc_vsx_stxvw4x:

llvm/test/CodeGen/PowerPC/vector-sum-sat-bit-side-effect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix-xcoff \
 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix-xcoff \
 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 
 define void @test1(<16 x i8> %0) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v3, v3, v3
-; CHECK-NEXT:    vsum4sbs v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)
   ret void
 }
 
 define void @test2(<8 x i16> %0) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v3, v3, v3
-; CHECK-NEXT:    vsum4shs v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)
   ret void
 }
 
 define void @test3(<16 x i8> %0) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v3, v3, v3
-; CHECK-NEXT:    vsum4ubs v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)
   ret void
 }
 
 define void @test4(<16 x i8> %0) {
 ; CHECK-LABEL: test4:

 entry:
   %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)
   ret <4 x i32> %1
 }
 
 define <4 x i32> @test10(<16 x i8> %0, <16 x i8> %1) {
 ; CHECK-LABEL: test10:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v4, v4, v4
-; CHECK-NEXT:    vsum4sbs v2, v2, v4
-; CHECK-NEXT:    vsum4sbs v3, v3, v4
+; CHECK-NEXT:    xxlxor v3, v3, v3
+; CHECK-NEXT:    vsum4sbs v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)
   %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %1, <4 x i32> zeroinitializer)
   ret <4 x i32> %2
 }
 
 define <4 x i32> @test11(<8 x i16> %0, <8 x i16> %1) {
 ; CHECK-LABEL: test11:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v4, v4, v4
-; CHECK-NEXT:    vsum4shs v2, v2, v4
-; CHECK-NEXT:    vsum4shs v3, v3, v4
+; CHECK-NEXT:    xxlxor v3, v3, v3
+; CHECK-NEXT:    vsum4shs v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)
   %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %1, <4 x i32> zeroinitializer)
   ret <4 x i32> %2
 }
 
 define <4 x i32> @test12(<16 x i8> %0, <16 x i8> %1) {
 ; CHECK-LABEL: test12:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v4, v4, v4
-; CHECK-NEXT:    vsum4ubs v2, v2, v4
-; CHECK-NEXT:    vsum4ubs v3, v3, v4
+; CHECK-NEXT:    xxlxor v3, v3, v3
+; CHECK-NEXT:    vsum4ubs v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)
   %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %1, <4 x i32> zeroinitializer)
   ret <4 x i32> %2
 }
 
 declare <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8>, <4 x i32>)
 declare <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16>, <4 x i32>)
 declare <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8>, <4 x i32>)