[InstCombine] Transform `(shift X,Or(Y,BitWidth-1))` -> `(shift X,BitWidth-1)`

[goldstein.w.n]

Summary

shl : https://alive2.llvm.org/ce/z/_B7Qca
lshr: https://alive2.llvm.org/ce/z/6eXz_W
ashr: https://alive2.llvm.org/ce/z/oGEx-q

[nikic]

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

492

Can also propagate the exact flag. At which point using replaceOperand() might actually be cleaner for once.

[goldstein.w.n]

Use replaceOperand to propegate exact flag + simplifiy logic

[nikic]

LGTM, but please precommit the tests.

[goldstein.w.n]

Split tests

[goldstein.w.n]

Rebase

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Constant(C))) &&
     Constant *Mask = ConstantExpr::getSub(C, ConstantInt::get(Ty, 1));
     Value *Rem = Builder.CreateAnd(A, Mask, Op1->getName());
     return replaceOperand(I, 1, Rem);
   }
 
   if (Instruction *Logic = foldShiftOfShiftedBinOp(I, Builder))
     return Logic;
 
+  if (match(Op1, m_Or(m_Value(), m_SpecificInt(BitWidth - 1))))
+    return replaceOperand(I, 1, ConstantInt::get(Ty, BitWidth - 1));
+
   return nullptr;
 }
 
 /// Return true if we can simplify two logical (either left or right) shifts
 /// that have constant shift amounts: OuterShift (InnerShift X, C1), C2.
 static bool canEvaluateShiftedShift(unsigned OuterShAmt, bool IsOuterShl,
                                     Instruction *InnerShift,
                                     InstCombinerImpl &IC, Instruction *CxtI) {
   assert(InnerShift->isLogicalShift() && "Unexpected instruction type");
 
   // We need constant scalar or constant splat shifts.
   const APInt *InnerShiftConst;

llvm/test/Transforms/InstCombine/shift.ll

;
   %tz = call i32 @llvm.cttz.i32(i32 %x, i1 true)
   %shl = shl i32 2, %tz
   ret i32 %shl
 }
 
 ; shift (X, amt | bitwidth - 1) -> shift (X, bitwidth - 1)
 define i6 @shl_or7_eq_shl7(i6 %x, i6 %c) {
 ; CHECK-LABEL: @shl_or7_eq_shl7(
-; CHECK-NEXT:    [[AMT:%.*]] = or i6 [[C:%.*]], 5
-; CHECK-NEXT:    [[Y:%.*]] = shl nsw i6 [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    [[Y:%.*]] = shl nsw i6 [[X:%.*]], 5
 ; CHECK-NEXT:    ret i6 [[Y]]
 ;
   %amt = or i6 %c, 5
   ;; nsw not needed for transform, just check that we propegate.
   %y = shl nsw i6 %x, %amt
   ret i6 %y
 }
 
 define <2 x i8> @lshr_vec_or7_eq_shl7(<2 x i8> %x, <2 x i8> %c) {
 ; CHECK-LABEL: @lshr_vec_or7_eq_shl7(
-; CHECK-NEXT:    [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
-; CHECK-NEXT:    [[Y:%.*]] = lshr exact <2 x i8> [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    [[Y:%.*]] = lshr exact <2 x i8> [[X:%.*]], <i8 7, i8 7>
 ; CHECK-NEXT:    ret <2 x i8> [[Y]]
 ;
   %amt = or <2 x i8> %c, <i8 7, i8 7>
   ;; exact not needed for transform, just check that we propegate.
   %y = lshr exact <2 x i8> %x, %amt
   ret <2 x i8> %y
 }
 
 define <2 x i8> @ashr_vec_or7_eq_ashr7(<2 x i8> %x, <2 x i8> %c) {
 ; CHECK-LABEL: @ashr_vec_or7_eq_ashr7(
-; CHECK-NEXT:    [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
-; CHECK-NEXT:    [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7>
 ; CHECK-NEXT:    ret <2 x i8> [[Y]]
 ;
   %amt = or <2 x i8> %c, <i8 7, i8 7>
   %y = ashr <2 x i8> %x, %amt
   ret <2 x i8> %y
 }
 
 ; Negative test not bitwidth - 1