This is an archive of the discontinued LLVM Phabricator instance.

Differential D144144

[X86] Add tests for combining mask with shuffles; NFC
ClosedPublic

Authored by goldstein.w.n on Feb 15 2023, 3:29 PM.

Details

Reviewers
RKSimon
pengfei
Commits
rGd821ac1aaf94: Add tests for combining mask with shuffles; NFC

Diff Detail

Unit TestsFailed

TimeTest
3,810 msx64 debian > LLVM.CodeGen/X86::combine-and.ll
3,590 msx64 debian > LLVM.CodeGen/X86::copy-low-subvec-elt-to-high-subvec-elt.ll
4,620 msx64 debian > LLVM.CodeGen/X86::haddsub-shuf.ll
4,350 msx64 debian > LLVM.CodeGen/X86::haddsub-undef.ll
3,350 msx64 debian > LLVM.CodeGen/X86::matrix-multiply.ll
View Full Test Results (59 Failed)

Event Timeline

goldstein.w.n created this revision.Feb 15 2023, 3:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 15 2023, 3:29 PM
Herald added a subscriber: pengfei. · View Herald Transcript
goldstein.w.n requested review of this revision.Feb 15 2023, 3:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 15 2023, 3:29 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
goldstein.w.n added a child revision: D143860: [X86] Add additional operations that masked instructions can combine with.Feb 15 2023, 3:30 PM
goldstein.w.n added reviewers: RKSimon, pengfei.
goldstein.w.n added a parent revision: D143789: [X86] Widen i16 shuffle masks if vector width < 512 even with BWI.
Harbormaster completed remote builds in B214007: Diff 497824.Feb 15 2023, 4:31 PM
goldstein.w.n updated this revision to Diff 497902.Feb 15 2023, 11:55 PM

Rebase

goldstein.w.n updated this revision to Diff 497911.Feb 16 2023, 12:33 AM

Rebase

Harbormaster completed remote builds in B214079: Diff 497911.Feb 16 2023, 2:50 AM
goldstein.w.n updated this revision to Diff 498075.Feb 16 2023, 10:31 AM

Rebase

Harbormaster completed remote builds in B214201: Diff 498075.Feb 16 2023, 12:28 PM
RKSimon accepted this revision.Feb 17 2023, 2:39 AM

LGTM

This revision is now accepted and ready to land.Feb 17 2023, 2:39 AM
goldstein.w.n updated this revision to Diff 499004.Feb 20 2023, 6:10 PM

Rebase

goldstein.w.n updated this revision to Diff 499028.Feb 20 2023, 7:53 PM

Rebase

Harbormaster completed remote builds in B214917: Diff 499028.Feb 20 2023, 10:37 PM
goldstein.w.n updated this revision to Diff 499387.Feb 21 2023, 11:41 PM

Rebase

Harbormaster completed remote builds in B215176: Diff 499387.Feb 22 2023, 12:35 AM
goldstein.w.n updated this revision to Diff 499549.Feb 22 2023, 9:16 AM

Rebase

Harbormaster completed remote builds in B215290: Diff 499549.Feb 22 2023, 12:02 PM
goldstein.w.n updated this revision to Diff 499699.Feb 22 2023, 5:43 PM

Rebase

Harbormaster completed remote builds in B215407: Diff 499699.Feb 22 2023, 7:51 PM
goldstein.w.n updated this revision to Diff 500066.Feb 23 2023, 8:11 PM

Rebase

Harbormaster completed remote builds in B215667: Diff 500066.Feb 23 2023, 10:55 PM
goldstein.w.n updated this revision to Diff 500310.Feb 24 2023, 3:11 PM

Rebase

goldstein.w.n updated this revision to Diff 500379.Feb 24 2023, 11:32 PM

Rebase

Harbormaster completed remote builds in B215898: Diff 500379.Feb 24 2023, 11:33 PM
goldstein.w.n updated this revision to Diff 500480.Feb 25 2023, 5:01 PM

Rebase

Harbormaster completed remote builds in B215982: Diff 500480.Feb 25 2023, 7:09 PM
Closed by commit rGd821ac1aaf94: Add tests for combining mask with shuffles; NFC (authored by goldstein.w.n). · Explain WhyFeb 26 2023, 10:12 AM
This revision was automatically updated to reflect the committed changes.
goldstein.w.n added a commit: rGd821ac1aaf94: Add tests for combining mask with shuffles; NFC.

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
229 lines

Diff 499387

llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vpopcntdq,+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK
define <16 x i32> @combine_mask_with_or(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_or:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpord %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = or <16 x i32> %shuf0_0, %shuf0_1
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_mul(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_mul:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpmulld %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = mul <16 x i32> %shuf0_0, %shuf0_1
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_abs(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_abs:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: vpabsd %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0_tmp0 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %shuf0_0, i1 true)
%op0_0_tmp1 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %shuf0_1, i1 true)
%op0_0 = shufflevector <16 x i32> %op0_0_tmp0, <16 x i32> %op0_0_tmp0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_umin(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_umin:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $-21846, %ax # imm = 0xAAAA
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpminud %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = tail call <16 x i32> @llvm.umin.v16i32(<16 x i32> %shuf0_0, <16 x i32> %shuf0_1)
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_umax(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_umax:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $-21846, %ax # imm = 0xAAAA
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpmaxud %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = tail call <16 x i32> @llvm.umax.v16i32(<16 x i32> %shuf0_0, <16 x i32> %shuf0_1)
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_smin(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_smin:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $-21846, %ax # imm = 0xAAAA
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpminsd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = tail call <16 x i32> @llvm.smin.v16i32(<16 x i32> %shuf0_0, <16 x i32> %shuf0_1)
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_smax(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_smax:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $-21846, %ax # imm = 0xAAAA
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpmaxsd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = tail call <16 x i32> @llvm.smax.v16i32(<16 x i32> %shuf0_0, <16 x i32> %shuf0_1)
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_shl(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_shl:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpsllvd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = shl <16 x i32> %shuf0_0, %shuf0_1
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_ashr(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_ashr:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpsravd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = ashr <16 x i32> %shuf0_0, %shuf0_1
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
define <16 x i32> @combine_mask_with_lshr(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_lshr:
; CHECK: # %bb.0:
; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpsrlvd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpopcntd %zmm0, %zmm0
; CHECK-NEXT: movb $-52, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf0_0 = shufflevector <16 x i32> %v0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
%shuf0_1 = shufflevector <16 x i32> %v0, <16 x i32> %shuf0_0, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
%op0_0 = lshr <16 x i32> %shuf0_0, %shuf0_1
%op1_0 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %v0)
%r = shufflevector <16 x i32> %op0_0, <16 x i32> %op1_0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
ret <16 x i32> %r
}
declare <16 x i32> @llvm.smin.v16i32(<16 x i32>, <16 x i32>)
declare <16 x i32> @llvm.smax.v16i32(<16 x i32>, <16 x i32>)
declare <16 x i32> @llvm.umin.v16i32(<16 x i32>, <16 x i32>)
declare <16 x i32> @llvm.umax.v16i32(<16 x i32>, <16 x i32>)
declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>)
declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)