[LoongArch] Make use of addu16i.d for adds with suitable immediates

[xen0n]

Summary

Ideally addu16i.d could be paired with {ld,st}ptr for faster memory
accesses with 32-bit-aligned offsets (it was designed for this purpose),
but it would require more work and the original use case (GP-relative
accesses) does not exist any more with the current LoongArch psABI.

It could still be used for accelerating additions of certain constants
though, which is what this patch intends to do.

[SixWeining]

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

186

Thanks.

Mabbe you can add these as baseline tests (no-functional-change or NFC patch) :)
https://github.com/llvm/llvm-project/blob/main/llvm/docs/TestingGuide.rst#precommit-workflow-for-tests

[xen0n]

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

186

Okay I'll split patches shortly. Thanks for the suggestion.

[xen0n]

Rebase & split tests out & implement matching of paired addu16i.d + addi patterns

[SixWeining]

Thanks for the improvements. LGTM. What do others think?

[gonglingqin]

LGTM. Thanks!

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 
 // A symbol or an imm used in BL/PseudoCALL/PseudoTAIL.
 def simm26_symbol : Operand<GRLenVT> {
   let ParserMatchClass = SImm26OperandBL;
   let EncoderMethod = "getImmOpValueAsr2";
   let DecoderMethod = "decodeSImmOperand<26, 2>";
 }
 
+// A 32-bit signed immediate with the lowest 16 bits zeroed, suitable for
+// direct use with `addu16i.d`.
+def simm16_lsl16 : Operand<GRLenVT>,
+    ImmLeaf<GRLenVT, [{return isShiftedInt<16, 16>(Imm);}]>;
+
+// A 32-bit signed immediate expressible with a pair of `addu16i.d + addi` for
+// use in additions.
+def simm32_hi16_lo12: Operand<GRLenVT>, ImmLeaf<GRLenVT, [{
+  return isShiftedInt<16, 16>(Imm - SignExtend64<12>(Imm));
+}]>;
+
 def BareSymbol : AsmOperandClass {
   let Name = "BareSymbol";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = "InvalidBareSymbol";
   let ParserMethod = "parseImmediate";
 }
 
 // A bare symbol used in "PseudoLA_*" instructions.

 def fpimm1    : PatLeaf<(fpimm), [{return N->isExactlyValue(+1.0);}]>;
 
 // Return an immediate subtracted from 32.
 def ImmSubFrom32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
+// Return the lowest 12 bits of the signed immediate.
+def LO12: SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(SignExtend64<12>(N->getSExtValue()),
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
+// Return the higher 16 bits of the signed immediate.
+def HI16 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue() >> 16, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+// Return the higher 16 bits of the signed immediate, adjusted for use within an
+// `addu16i.d + addi` pair.
+def HI16ForAddu16idAddiPair: SDNodeXForm<imm, [{
+  auto Imm = N->getSExtValue();
+  return CurDAG->getTargetConstant((Imm - SignExtend64<12>(Imm)) >> 16,
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
 def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
 def AddrConstant : ComplexPattern<iPTR, 2, "SelectAddrConstant">;
 def NonFIBaseAddr : ComplexPattern<iPTR, 1, "selectNonFIBaseAddr">;
 
 def fma_nsz : PatFrag<(ops node:$fj, node:$fk, node:$fa),
                       (fma node:$fj, node:$fk, node:$fa), [{
   return N->getFlags().hasNoSignedZeros();
 }]>;

 // multiplication.
 def : Pat<(i64 (mul (sext_inreg GPR:$rj, i32), (sext_inreg GPR:$rk, i32))),
           (MULW_D_W GPR:$rj, GPR:$rk)>;
 // Select MULW_D_WU for calculating the full 64 bits product of i32xi32
 // unsigned multiplication.
 def : Pat<(i64 (mul (loongarch_bstrpick GPR:$rj, (i64 31), (i64 0)),
                     (loongarch_bstrpick GPR:$rk, (i64 31), (i64 0)))),
           (MULW_D_WU GPR:$rj, GPR:$rk)>;
+
+def : Pat<(add GPR:$rj, simm16_lsl16:$imm),
+          (ADDU16I_D GPR:$rj, (HI16 $imm))>;
+def : Pat<(add GPR:$rj, simm32_hi16_lo12:$imm),
+          (ADDI_D (ADDU16I_D GPR:$rj, (HI16ForAddu16idAddiPair $imm)),
+                  (LO12 $imm))>;
+def : Pat<(sext_inreg (add GPR:$rj, simm32_hi16_lo12:$imm), i32),
+          (ADDI_W (ADDU16I_D GPR:$rj, (HI16ForAddu16idAddiPair $imm)),
+                  (LO12 $imm))>;
 } // Predicates = [IsLA64]
 
 def : PatGprGpr<and, AND>;
 def : PatGprImm<and, ANDI, uimm12>;
 def : PatGprGpr<or, OR>;
 def : PatGprImm<or, ORI, uimm12>;
 def : PatGprGpr<xor, XOR>;
 def : PatGprImm<xor, XORI, uimm12>;

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

 ; LA64-LABEL: add_i64_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, 3
 ; LA64-NEXT:    ret
   %add = add i64 %x, 3
   ret i64 %add
 }
 
-;; TODO: emit `addu16i.d` for these cases.
+;; Check that `addu16i.d` is emitted for these cases.
 
 define i32 @add_i32_0x12340000(i32 %x) {
 ; LA32-LABEL: add_i32_0x12340000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 74560
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x12340000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 74560
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 4660
 ; LA64-NEXT:    ret
   %add = add i32 %x, 305397760
   ret i32 %add
 }
 
 define signext i32 @add_i32_0x12340000_sext(i32 %x) {
 ; LA32-LABEL: add_i32_0x12340000_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 74560
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x12340000_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 74560
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 4660
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    ret
   %add = add i32 %x, 305397760
   ret i32 %add
 }
 
 define i64 @add_i64_0x12340000(i64 %x) {
 ; LA32-LABEL: add_i64_0x12340000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 74560
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_0x12340000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 74560
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 4660
 ; LA64-NEXT:    ret
   %add = add i64 %x, 305397760
   ret i64 %add
 }
 
 define i32 @add_i32_0x7fff0000(i32 %x) {
 ; LA32-LABEL: add_i32_0x7fff0000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 524272
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x7fff0000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524272
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
 ; LA64-NEXT:    ret
   %add = add i32 %x, 2147418112
   ret i32 %add
 }
 
 define signext i32 @add_i32_0x7fff0000_sext(i32 %x) {
 ; LA32-LABEL: add_i32_0x7fff0000_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 524272
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x7fff0000_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524272
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    ret
   %add = add i32 %x, 2147418112
   ret i32 %add
 }
 
 define i64 @add_i64_0x7fff0000(i64 %x) {
 ; LA32-LABEL: add_i64_0x7fff0000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 524272
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_0x7fff0000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524272
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
 ; LA64-NEXT:    ret
   %add = add i64 %x, 2147418112
   ret i64 %add
 }
 
 define i32 @add_i32_minus_0x80000000(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x80000000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -524288
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x80000000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -524288
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -32768
 ; LA64-NEXT:    ret
   %add = add i32 %x, -2147483648
   ret i32 %add
 }
 
 define signext i32 @add_i32_minus_0x80000000_sext(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x80000000_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -524288
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x80000000_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -524288
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -32768
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    ret
   %add = add i32 %x, -2147483648
   ret i32 %add
 }
 
 define i64 @add_i64_minus_0x80000000(i64 %x) {
 ; LA32-LABEL: add_i64_minus_0x80000000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, -524288
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_0x80000000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -524288
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -32768
 ; LA64-NEXT:    ret
   %add = add i64 %x, -2147483648
   ret i64 %add
 }
 
 define i32 @add_i32_minus_0x10000(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x10000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -16
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x10000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -16
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -1
 ; LA64-NEXT:    ret
   %add = add i32 %x, -65536
   ret i32 %add
 }
 
 define signext i32 @add_i32_minus_0x10000_sext(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x10000_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -16
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x10000_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -16
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -1
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    ret
   %add = add i32 %x, -65536
   ret i32 %add
 }
 
 define i64 @add_i64_minus_0x10000(i64 %x) {
 ; LA32-LABEL: add_i64_minus_0x10000:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, -16
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_0x10000:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -16
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -1
 ; LA64-NEXT:    ret
   %add = add i64 %x, -65536
   ret i64 %add
 }
 
-;; TODO: use `addu16i.d + addi` for these cases.
+;; Check that `addu16i.d + addi` is emitted for these cases.
 
 define i32 @add_i32_0x7fff07ff(i32 %x) {
 ; LA32-LABEL: add_i32_0x7fff07ff:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 524272
 ; LA32-NEXT:    ori $a1, $a1, 2047
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x7fff07ff:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524272
-; LA64-NEXT:    ori $a1, $a1, 2047
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
+; LA64-NEXT:    addi.d $a0, $a0, 2047
 ; LA64-NEXT:    ret
   %add = add i32 %x, 2147420159
   ret i32 %add
 }
 
 define signext i32 @add_i32_0x7fff07ff_sext(i32 %x) {
 ; LA32-LABEL: add_i32_0x7fff07ff_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 524272
 ; LA32-NEXT:    ori $a1, $a1, 2047
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x7fff07ff_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524272
-; LA64-NEXT:    ori $a1, $a1, 2047
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
+; LA64-NEXT:    addi.w $a0, $a0, 2047
 ; LA64-NEXT:    ret
   %add = add i32 %x, 2147420159
   ret i32 %add
 }
 
 define i64 @add_i64_0x7fff07ff(i64 %x) {
 ; LA32-LABEL: add_i64_0x7fff07ff:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 524272
 ; LA32-NEXT:    ori $a2, $a2, 2047
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_0x7fff07ff:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524272
-; LA64-NEXT:    ori $a1, $a1, 2047
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
+; LA64-NEXT:    addi.d $a0, $a0, 2047
 ; LA64-NEXT:    ret
   %add = add i64 %x, 2147420159
   ret i64 %add
 }
 
 define i32 @add_i32_0x7ffef800(i32 %x) {
 ; LA32-LABEL: add_i32_0x7ffef800:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 524271
 ; LA32-NEXT:    ori $a1, $a1, 2048
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x7ffef800:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524271
-; LA64-NEXT:    ori $a1, $a1, 2048
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
+; LA64-NEXT:    addi.d $a0, $a0, -2048
 ; LA64-NEXT:    ret
   %add = add i32 %x, 2147416064
   ret i32 %add
 }
 
 define signext i32 @add_i32_0x7ffef800_sext(i32 %x) {
 ; LA32-LABEL: add_i32_0x7ffef800_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 524271
 ; LA32-NEXT:    ori $a1, $a1, 2048
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_0x7ffef800_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524271
-; LA64-NEXT:    ori $a1, $a1, 2048
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
+; LA64-NEXT:    addi.w $a0, $a0, -2048
 ; LA64-NEXT:    ret
   %add = add i32 %x, 2147416064
   ret i32 %add
 }
 
 define i64 @add_i64_0x7ffef800(i64 %x) {
 ; LA32-LABEL: add_i64_0x7ffef800:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 524271
 ; LA32-NEXT:    ori $a2, $a2, 2048
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_0x7ffef800:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524271
-; LA64-NEXT:    ori $a1, $a1, 2048
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, 32767
+; LA64-NEXT:    addi.d $a0, $a0, -2048
 ; LA64-NEXT:    ret
   %add = add i64 %x, 2147416064
   ret i64 %add
 }
 
 define i64 @add_i64_minus_0x80000800(i64 %x) {
 ; LA32-LABEL: add_i64_minus_0x80000800:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, 524287
 ; LA32-NEXT:    ori $a2, $a2, 2048
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_0x80000800:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, 524287
-; LA64-NEXT:    ori $a1, $a1, 2048
-; LA64-NEXT:    lu32i.d $a1, -1
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -32768
+; LA64-NEXT:    addi.d $a0, $a0, -2048
 ; LA64-NEXT:    ret
   %add = add i64 %x, -2147485696
   ret i64 %add
 }
 
 define i32 @add_i32_minus_0x23450679(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x23450679:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -144465
 ; LA32-NEXT:    ori $a1, $a1, 2439
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x23450679:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -144465
-; LA64-NEXT:    ori $a1, $a1, 2439
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -9029
+; LA64-NEXT:    addi.d $a0, $a0, -1657
 ; LA64-NEXT:    ret
   %add = add i32 %x, -591726201
   ret i32 %add
 }
 
 define signext i32 @add_i32_minus_0x23450679_sext(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x23450679_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -144465
 ; LA32-NEXT:    ori $a1, $a1, 2439
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x23450679_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -144465
-; LA64-NEXT:    ori $a1, $a1, 2439
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -9029
+; LA64-NEXT:    addi.w $a0, $a0, -1657
 ; LA64-NEXT:    ret
   %add = add i32 %x, -591726201
   ret i32 %add
 }
 
 define i64 @add_i64_minus_0x23450679(i64 %x) {
 ; LA32-LABEL: add_i64_minus_0x23450679:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, -144465
 ; LA32-NEXT:    ori $a2, $a2, 2439
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_0x23450679:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -144465
-; LA64-NEXT:    ori $a1, $a1, 2439
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -9029
+; LA64-NEXT:    addi.d $a0, $a0, -1657
 ; LA64-NEXT:    ret
   %add = add i64 %x, -591726201
   ret i64 %add
 }
 
 define i32 @add_i32_minus_0x2345fedd(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x2345fedd:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -144480
 ; LA32-NEXT:    ori $a1, $a1, 291
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x2345fedd:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -144480
-; LA64-NEXT:    ori $a1, $a1, 291
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -9030
+; LA64-NEXT:    addi.d $a0, $a0, 291
 ; LA64-NEXT:    ret
   %add = add i32 %x, -591789789
   ret i32 %add
 }
 
 define signext i32 @add_i32_minus_0x2345fedd_sext(i32 %x) {
 ; LA32-LABEL: add_i32_minus_0x2345fedd_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, -144480
 ; LA32-NEXT:    ori $a1, $a1, 291
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_0x2345fedd_sext:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -144480
-; LA64-NEXT:    ori $a1, $a1, 291
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -9030
+; LA64-NEXT:    addi.w $a0, $a0, 291
 ; LA64-NEXT:    ret
   %add = add i32 %x, -591789789
   ret i32 %add
 }
 
 define i64 @add_i64_minus_0x2345fedd(i64 %x) {
 ; LA32-LABEL: add_i64_minus_0x2345fedd:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a2, -144480
 ; LA32-NEXT:    ori $a2, $a2, 291
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_0x2345fedd:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -144480
-; LA64-NEXT:    ori $a1, $a1, 291
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addu16i.d $a0, $a0, -9030
+; LA64-NEXT:    addi.d $a0, $a0, 291
 ; LA64-NEXT:    ret
   %add = add i64 %x, -591789789
   ret i64 %add
 }
 
 ;; Check that `addu16i.d` isn't used for the following cases.
 
 define i64 @add_i64_0x80000000(i64 %x) {