[mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions

[hvarga]

Summary

The patch implements microMIPSDSP instructions: MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH, MULQ_S.W.

[dsanders]

LGTM with a small test change

lib/Target/Mips/MicroMipsDSPInstrInfo.td

69 ↗

(On Diff #39043)

Formatting nit: Bring back the space after '//' and the '.'

test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

18–22 ↗

(On Diff #39043)

The DSPr1 tests should also be present. Likewise for the assembler tests.

See my comment on D14058 for more info.

[hvarga]

Standard encoding tests will be a separate task.

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td

 class DPS_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dps.w.ph", 0b00010010>;
 class DPSQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpsq_s.w.ph", 0b00011010>;
 class DPSQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpsq_sa.l.w", 0b01011010>;
 class DPSQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_s.w.ph", 0b10011010>;
 class DPSQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_sa.w.ph", 0b11011010>;
 class DPSU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbl", 0b10010010>;
 class DPSU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbr", 0b11010010>;
 class DPSX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsx.w.ph", 0b01010010>;
+class MUL_PH_MMR2_ENC : POOL32A_3R_FMT<"mul.ph", 0b00000101101>;
+class MUL_S_PH_MMR2_ENC : POOL32A_3R_FMT<"mul_s.ph", 0b10000101101>;
+class MULEQ_S_W_PHL_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phl", 0b0000100101>;
+class MULEQ_S_W_PHR_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phr", 0b0001100101>;
+class MULEU_S_PH_QBL_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbl", 0b0010010101>;
+class MULEU_S_PH_QBR_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbr", 0b0011010101>;
+class MULQ_RS_PH_MM_ENC : POOL32A_3RB0_FMT<"mulq_rs.ph", 0b0100010101>;
+class MULQ_RS_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_rs.w", 0b0110010101>;
+class MULQ_S_PH_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.ph", 0b0101010101>;
+class MULQ_S_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.w", 0b0111010101>;
 
 // Instruction desc.
 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
                                 InstrItinClass itin, RegisterOperand ROD,
                                 RegisterOperand ROS = ROD> {
   dag OutOperandList = (outs ROD:$rt);
   dag InOperandList = (ins ROS:$rs);
   string AsmString = !strconcat(opstr, "\t$rt, $rs");

 def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC;
 def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC;
 def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC;
 def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC;
 def DPSQ_S_W_PH_MM : DspMMRel, DPSQ_S_W_PH_MM_ENC, DPSQ_S_W_PH_DESC;
 def DPSQ_SA_L_W_MM : DspMMRel, DPSQ_SA_L_W_MM_ENC, DPSQ_SA_L_W_DESC;
 def DPSU_H_QBL_MM : DspMMRel, DPSU_H_QBL_MM_ENC, DPSU_H_QBL_DESC;
 def DPSU_H_QBR_MM : DspMMRel, DPSU_H_QBR_MM_ENC, DPSU_H_QBR_DESC;
+def MULEQ_S_W_PHL_MM : DspMMRel, MULEQ_S_W_PHL_MM_ENC, MULEQ_S_W_PHL_DESC;
+def MULEQ_S_W_PHR_MM : DspMMRel, MULEQ_S_W_PHR_MM_ENC, MULEQ_S_W_PHR_DESC;
+def MULEU_S_PH_QBL_MM : DspMMRel, MULEU_S_PH_QBL_MM_ENC, MULEU_S_PH_QBL_DESC;
+def MULEU_S_PH_QBR_MM : DspMMRel, MULEU_S_PH_QBR_MM_ENC, MULEU_S_PH_QBR_DESC;
+def MULQ_RS_PH_MM : DspMMRel, MULQ_RS_PH_MM_ENC, MULQ_RS_PH_DESC;
 // microMIPS DSP Rev 2
 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
                      ISA_DSPR2;
 def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
 def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
 def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
 def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
 def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;

 def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2;
 def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
 def DPS_W_PH_MMR2 : DspMMRel, DPS_W_PH_MMR2_ENC, DPS_W_PH_DESC, ISA_DSPR2;
 def DPSQX_S_W_PH_MMR2 : DspMMRel, DPSQX_S_W_PH_MMR2_ENC, DPSQX_S_W_PH_DESC,
                         ISA_DSPR2;
 def DPSQX_SA_W_PH_MMR2 : DspMMRel, DPSQX_SA_W_PH_MMR2_ENC, DPSQX_SA_W_PH_DESC,
                          ISA_DSPR2;
 def DPSX_W_PH_MMR2 : DspMMRel, DPSX_W_PH_MMR2_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
+def MUL_PH_MMR2 : DspMMRel, MUL_PH_MMR2_ENC, MUL_PH_DESC, ISA_DSPR2;
+def MUL_S_PH_MMR2 : DspMMRel, MUL_S_PH_MMR2_ENC, MUL_S_PH_DESC, ISA_DSPR2;
+def MULQ_RS_W_MMR2 : DspMMRel, MULQ_RS_W_MMR2_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
+def MULQ_S_PH_MMR2 : DspMMRel, MULQ_S_PH_MMR2_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
+def MULQ_S_W_MMR2 : DspMMRel, MULQ_S_W_MMR2_ENC, MULQ_S_W_DESC, ISA_DSPR2;

llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td

 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
-def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
-def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
-def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
-def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
-def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
+def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
+def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
+def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
+def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
+def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
 def MTHI_DSP : MTHI_ENC, MTHI_DESC;

 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
-def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
-def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
-def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
-def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
-def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
+def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC;
+def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC;
+def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC;
+def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC;
+def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC;
 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;

llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

 0x00 0xa4 0x1e 0x0d # CHECK: subq_s.ph $3, $4, $5
 0x00 0xa4 0x1b 0x45 # CHECK: subq_s.w $3, $4, $5
 0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5
 0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5
 0x00 0xc4 0x46 0xbc # CHECK: dpsq_s.w.ph $ac1, $4, $6
 0x00 0xc4 0x56 0xbc # CHECK: dpsq_sa.l.w $ac1, $4, $6
 0x00 0xc4 0x64 0xbc # CHECK: dpsu.h.qbl $ac1, $4, $6
 0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6
+0x00 0x62 0x08 0x25 # CHECK: muleq_s.w.phl $1, $2, $3
+0x00 0x62 0x08 0x65 # CHECK: muleq_s.w.phr $1, $2, $3
+0x00 0x62 0x08 0x95 # CHECK: muleu_s.ph.qbl $1, $2, $3
+0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
+0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3

llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

 0x00 0xc4 0x46 0xbc # CHECK: dpsq_s.w.ph $ac1, $4, $6
 0x00 0xc4 0x56 0xbc # CHECK: dpsq_sa.l.w $ac1, $4, $6
 0x00 0xc4 0x64 0xbc # CHECK: dpsu.h.qbl $ac1, $4, $6
 0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6
 0x00 0xc4 0x44 0xbc # CHECK: dps.w.ph $ac1, $4, $6
 0x00 0xc4 0x66 0xbc # CHECK: dpsqx_s.w.ph $ac1, $4, $6
 0x00 0xc4 0x76 0xbc # CHECK: dpsqx_sa.w.ph $ac1, $4, $6
 0x00 0xc4 0x54 0xbc # CHECK: dpsx.w.ph $ac1, $4, $6
+0x00 0x62 0x08 0x2d # CHECK: mul.ph $1, $2, $3
+0x00 0x62 0x0c 0x2d # CHECK: mul_s.ph $1, $2, $3
+0x00 0x62 0x09 0x95 # CHECK: mulq_rs.w $1, $2, $3
+0x00 0x62 0x09 0x55 # CHECK: mulq_s.ph $1, $2, $3
+0x00 0x62 0x09 0xd5 # CHECK: mulq_s.w $1, $2, $3
+0x00 0x62 0x08 0x25 # CHECK: muleq_s.w.phl $1, $2, $3
+0x00 0x62 0x08 0x65 # CHECK: muleq_s.w.phr $1, $2, $3
+0x00 0x62 0x08 0x95 # CHECK: muleu_s.ph.qbl $1, $2, $3
+0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
+0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3

llvm/trunk/test/MC/Mips/micromips-dsp/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
   subq_s.ph $3, $4, $5         # CHECK: subq_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0x0d]
   subq_s.w $3, $4, $5          # CHECK: subq_s.w $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x45]
   subu.qb $3, $4, $5           # CHECK: subu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xcd]
   subu_s.qb $3, $4, $5         # CHECK: subu_s.qb $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0xcd]
   dpsq_s.w.ph $ac1, $4, $6     # CHECK: dpsq_s.w.ph $ac1, $4, $6   # encoding: [0x00,0xc4,0x46,0xbc]
   dpsq_sa.l.w $ac1, $4, $6     # CHECK: dpsq_sa.l.w $ac1, $4, $6   # encoding: [0x00,0xc4,0x56,0xbc]
   dpsu.h.qbl $ac1, $4, $6      # CHECK: dpsu.h.qbl $ac1, $4, $6    # encoding: [0x00,0xc4,0x64,0xbc]
   dpsu.h.qbr $ac1, $4, $6      # CHECK: dpsu.h.qbr $ac1, $4, $6    # encoding: [0x00,0xc4,0x74,0xbc]
+  muleq_s.w.phl $1, $2, $3     # CHECK: muleq_s.w.phl $1, $2, $3   # encoding: [0x00,0x62,0x08,0x25]
+  muleq_s.w.phr $1, $2, $3     # CHECK: muleq_s.w.phr $1, $2, $3   # encoding: [0x00,0x62,0x08,0x65]
+  muleu_s.ph.qbl $1, $2, $3    # CHECK: muleu_s.ph.qbl $1, $2, $3  # encoding: [0x00,0x62,0x08,0x95]
+  muleu_s.ph.qbr $1, $2, $3    # CHECK: muleu_s.ph.qbr $1, $2, $3  # encoding: [0x00,0x62,0x08,0xd5]
+  mulq_rs.ph $1, $2, $3        # CHECK: mulq_rs.ph $1, $2, $3      # encoding: [0x00,0x62,0x09,0x15]

llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
   dpsq_s.w.ph $ac1, $4, $6     # CHECK: dpsq_s.w.ph $ac1, $4, $6   # encoding: [0x00,0xc4,0x46,0xbc]
   dpsq_sa.l.w $ac1, $4, $6     # CHECK: dpsq_sa.l.w $ac1, $4, $6   # encoding: [0x00,0xc4,0x56,0xbc]
   dpsu.h.qbl $ac1, $4, $6      # CHECK: dpsu.h.qbl $ac1, $4, $6    # encoding: [0x00,0xc4,0x64,0xbc]
   dpsu.h.qbr $ac1, $4, $6      # CHECK: dpsu.h.qbr $ac1, $4, $6    # encoding: [0x00,0xc4,0x74,0xbc]
   dps.w.ph $ac1, $4, $6        # CHECK: dps.w.ph $ac1, $4, $6      # encoding: [0x00,0xc4,0x44,0xbc]
   dpsqx_s.w.ph $ac1, $4, $6    # CHECK: dpsqx_s.w.ph $ac1, $4, $6  # encoding: [0x00,0xc4,0x66,0xbc]
   dpsqx_sa.w.ph $ac1, $4, $6   # CHECK: dpsqx_sa.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x76,0xbc]
   dpsx.w.ph $ac1, $4, $6       # CHECK: dpsx.w.ph $ac1, $4, $6     # encoding: [0x00,0xc4,0x54,0xbc]
+  mul.ph $1, $2, $3            # CHECK: mul.ph $1, $2, $3      # encoding: [0x00,0x62,0x08,0x2d]
+  mul_s.ph $1, $2, $3          # CHECK: mul_s.ph $1, $2, $3    # encoding: [0x00,0x62,0x0c,0x2d]
+  mulq_rs.w $1, $2, $3         # CHECK: mulq_rs.w $1, $2, $3   # encoding: [0x00,0x62,0x09,0x95]
+  mulq_s.ph $1, $2, $3         # CHECK: mulq_s.ph $1, $2, $3   # encoding: [0x00,0x62,0x09,0x55]
+  mulq_s.w $1, $2, $3          # CHECK: mulq_s.w $1, $2, $3    # encoding: [0x00,0x62,0x09,0xd5]
+  muleq_s.w.phl $1, $2, $3     # CHECK: muleq_s.w.phl $1, $2, $3   # encoding: [0x00,0x62,0x08,0x25]
+  muleq_s.w.phr $1, $2, $3     # CHECK: muleq_s.w.phr $1, $2, $3   # encoding: [0x00,0x62,0x08,0x65]
+  muleu_s.ph.qbl $1, $2, $3    # CHECK: muleu_s.ph.qbl $1, $2, $3  # encoding: [0x00,0x62,0x08,0x95]
+  muleu_s.ph.qbr $1, $2, $3    # CHECK: muleu_s.ph.qbr $1, $2, $3  # encoding: [0x00,0x62,0x08,0xd5]
+  mulq_rs.ph $1, $2, $3        # CHECK: mulq_rs.ph $1, $2, $3      # encoding: [0x00,0x62,0x09,0x15]