[AVR] Optimize 16-bit comparison with a constant

[benshi001]

Summary

Fixes https://github.com/llvm/llvm-project/issues/30923

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

659

Only a zero constant with be put at left by previous DAG transform, all other non-zero constant are dropped as RHS. So we have to handle it specially.

llvm/test/CodeGen/AVR/cmp.ll

213

x > 0 is compiled to 0 < x, and the low 0 value byte and the high 0 value byte are represented by the zero register.

[benshi001]

llvm/test/CodeGen/AVR/cmp.ll

232

x > 126 is compiled to x >= 127, the low byte value is 127, and the high byte valued zero is represented via the zero register.

252

x > 1023 is compiled to x >= 1024, the high byte is 4, and the low byte is represented via the zero register.

[benshi001]

llvm/test/CodeGen/AVR/cmp.ll

243

x > 126 is compiled to x >= 127, the low byte value is 127, and the high byte valued zero is represented via the zero register.

289

x > 1023 is compiled to x >= 1024, the high byte is 4, and the low byte is represented via the zero register.

[jacquesguan]

LGTM.

llvm/lib/Target/AVR/AVRISelLowering.cpp

assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
          "LHS and RHS have different types");
   assert(((LHS.getSimpleValueType() == MVT::i16) ||
           (LHS.getSimpleValueType() == MVT::i8)) &&
          "invalid comparison type");
 
   SDValue Cmp;
 
   if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
+    uint64_t Imm = cast<ConstantSDNode>(RHS)->getZExtValue();
     // Generate a CPI/CPC pair if RHS is a 16-bit constant.
     SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
                                 DAG.getIntPtrConstant(0, DL));
     SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
                                 DAG.getIntPtrConstant(1, DL));
+    SDValue RHSlo, RHShi;
+    if ((Imm & 0xff) != 0)
+      RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
+                          DAG.getIntPtrConstant(0, DL));
+    else // Use the zero register instead of a zero immediate.
+      RHSlo = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
+    if ((Imm & 0xff00) != 0)
+      RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
+                          DAG.getIntPtrConstant(1, DL));
+    else // Use the zero register instead of a zero immediate.
+      RHShi = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
+    Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
+    Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
+  } else if (RHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(LHS)) {
+    uint64_t Imm = cast<ConstantSDNode>(LHS)->getZExtValue();
+    if (Imm != 0)
+      llvm_unreachable("unexpected i16 comparison node");
+    // Generate a CPI/CPC pair.
+    SDValue LHSlo = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
+    SDValue LHShi = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
     SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
                                 DAG.getIntPtrConstant(0, DL));
     SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
                                 DAG.getIntPtrConstant(1, DL));
     Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
     Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
   } else {
     // Generate ordinary 16-bit comparison.

llvm/test/CodeGen/AVR/cmp.ll

 ; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mcpu=attiny10 | FileCheck --check-prefix=TINY %s
 
 declare void @f1(i8)
 declare void @f2(i8)
 define void @cmp8(i8 %a, i8 %b) {
 ; CHECK-LABEL: cmp8:
 ; CHECK: cp
 ; CHECK-NOT: cpc
   %cmp = icmp eq i8 %a, %b
if.then:
   tail call void @f9()
   br label %if.end
 if.else:
   tail call void @f10()
   br label %if.end
 if.end:
   ret void
 }
+
+define i16 @cmp_i16_gt_0(i16 %0) {
+; CHECK-LABEL: cmp_i16_gt_0:
+; CHECK:       %bb.0:
+; CHECK-NEXT:    ldi r18, 1
+; CHECK-NEXT:    cp  r1, r24
+; CHECK-NEXT:    cpc r1, r25
+; CHECK-NEXT:    brlt
+;
+; TINY-LABEL: cmp_i16_gt_0:
+; TINY:       %bb.0:
+; TINY-NEXT:    ldi r20, 1
+; TINY-NEXT:    cp  r17, r24
+; TINY-NEXT:    cpc r17, r25
+; TINY-NEXT:    brlt
+  %2 = icmp sgt i16 %0, 0
+  %3 = zext i1 %2 to i16
+  ret i16 %3
+}
+
+define i16 @cmp_i16_gt_126(i16 %0) {
+; CHECK-LABEL: cmp_i16_gt_126:
+; CHECK:       %bb.0:
+; CHECK-NEXT:    ldi  r18, 1
+; CHECK-NEXT:    cpi  r24, 127
+; CHECK-NEXT:    cpc  r25, r1
+; CHECK-NEXT:    brge
+;
+; TINY-LABEL: cmp_i16_gt_126:
+; TINY:       %bb.0:
+; TINY-NEXT:    ldi  r20, 1
+; TINY-NEXT:    cpi  r24, 127
+; TINY-NEXT:    cpc  r25, r17
+; TINY-NEXT:    brge
+  %2 = icmp sgt i16 %0, 126
+  %3 = zext i1 %2 to i16
+  ret i16 %3
+}
+
+define i16 @cmp_i16_gt_1023(i16 %0) {
+; CHECK-LABEL: cmp_i16_gt_1023:
+; CHECK:       %bb.0:
+; CHECK-NEXT:    ldi  r19, 4
+; CHECK-NEXT:    ldi  r18, 1
+; CHECK-NEXT:    cp   r24, r1
+; CHECK-NEXT:    cpc  r25, r19
+; CHECK-NEXT:    brge
+;
+; TINY-LABEL: cmp_i16_gt_1023:
+; TINY:       %bb.0:
+; TINY-NEXT:    ldi  r21, 4
+; TINY-NEXT:    ldi  r20, 1
+; TINY-NEXT:    cp   r24, r17
+; TINY-NEXT:    cpc  r25, r21
+; TINY-NEXT:    brge
+  %2 = icmp sgt i16 %0, 1023
+  %3 = zext i1 %2 to i16
+  ret i16 %3
+}