[AVR] Fix an issue of writing 16-bit ports

[benshi001]

Summary

For 16-bit ports, the normal devices reqiure writing high byte first
and then low byte. But the XMEGA devices require the reverse order.

Fixes https://github.com/llvm/llvm-project/issues/58395

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1404

I like this form

Low bound <= variable && variable <= high bound.

Rather then

variable' <= Low bound` && variable <= high bound.

which looks like variable is in range [low, high].

[aykevl]

This works for the out instruction, but what about a regular volatile store? I think it should be changed in the same way.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1402–1403

I think this is usually done via subtarget flags, not by looking at e_flags. I couldn't easily find something similar in other targets. But this also works.

[benshi001]

In D141752#4065457, @aykevl wrote:

This works for the out instruction, but what about a regular volatile store? I think it should be changed in the same way.

I have done for both OUTW and STSWKRr. Thanks!

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1402–1403

I have added a new target feature FeatureLowByteFirst and all XMEGA families contains this new feature.

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1138

We disallow post increment store for 16-bit store on ordinary AVRs, while the XMEGA devices are still allowed.

[benshi001]

All four pseudo instructions are modified : OUTW, STSWKRr, STDWPtrQRr, STWPtrRr.

[benshi001]

Unfortunately many tests are affected, fortunately the only change is exchanging the order of a store pair. ^_^

[benshi001]

We can see the full affection in the four pseudo instruction's .mir tests.

[benshi001]

llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir

24

The only difference between CHECK and CHECK-XMEGA is the order.

[benshi001]

ping ...

[benshi001]

ping ...

[benshi001]

ping ...

[jacquesguan]

LGTM.

llvm/lib/Target/AVR/AVRDevices.td

def FeatureBREAK : SubtargetFeature<"break", "m_hasBREAK", "true",
                                     "instruction">;
 
 // The device has instruction encodings specific to the Tiny core.
 def FeatureTinyEncoding
     : SubtargetFeature<"tinyencoding", "m_hasTinyEncoding", "true",
                        "The device has Tiny core specific "
                        "instruction encodings">;
 
+// When writing a 16-bit port or storing a 16-bit word, do the low byte first.
+def FeatureLowByteFirst
+    : SubtargetFeature<"lowbytefirst", "m_hasLowByteFirst", "true",
+                       "Do the low byte first when writing a 16-bit port or "
+                       "storing a 16-bit word">;
+
 // The device has CPU registers mapped in data address space
 def FeatureMMR : SubtargetFeature<"memmappedregs", "m_hasMemMappedGPR", "true",
                                   "The device has CPU registers "
                                   "mapped in data address space">;
 
 class ELFArch<string name>
     : SubtargetFeature<"", "ELFArch", !strconcat("ELF::", name), "">;
 
def FamilyTiny
     : Family<"avrtiny",
              [FamilyAVR0, FeatureBREAK, FeatureSRAM, FeatureTinyEncoding,
               FeatureSmallStack]>;
 
 def FamilyXMEGA3 : Family<"xmega3",
                           [FamilyAVR0, FeatureLPM, FeatureIJMPCALL,
                            FeatureADDSUBIW, FeatureSRAM, FeatureJMPCALL,
                            FeatureMultiplication, FeatureMOVW, FeatureLPMX,
-                           FeatureBREAK]>;
+                           FeatureBREAK, FeatureLowByteFirst]>;
 
 def FamilyXMEGA : Family<"xmega",
                          [FamilyAVR0, FeatureLPM, FeatureIJMPCALL,
                           FeatureADDSUBIW, FeatureSRAM, FeatureJMPCALL,
                           FeatureMultiplication, FeatureMOVW, FeatureLPMX,
                           FeatureSPM, FeatureBREAK, FeatureEIJMPCALL,
-                          FeatureSPMX, FeatureDES, FeatureELPM, FeatureELPMX]>;
+                          FeatureSPMX, FeatureDES, FeatureELPM, FeatureELPMX,
+                          FeatureLowByteFirst]>;
 
 def FamilyXMEGAU : Family<"xmegau", [FamilyXMEGA, FeatureRMW]>;
 
 def FeatureSetSpecial
     : FeatureSet<"special",
                  "Enable use of the entire instruction "
                  "set - used for debugging",
                  [

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

 bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
   // On AVR, there is only one core and so atomic fences do nothing.
   MBBI->eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
   MachineInstr &MI = *MBBI;
   Register SrcLoReg, SrcHiReg;
   Register SrcReg = MI.getOperand(1).getReg();
   bool SrcIsKill = MI.getOperand(1).isKill();
-  unsigned OpLo = AVR::STSKRr;
-  unsigned OpHi = AVR::STSKRr;
   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
-  // Write the high byte first in case this address belongs to a special
-  // I/O address with a special temporary register.
-  auto MIBHI = buildMI(MBB, MBBI, OpHi);
-  auto MIBLO = buildMI(MBB, MBBI, OpLo);
+  auto MIB0 = buildMI(MBB, MBBI, AVR::STSKRr);
+  auto MIB1 = buildMI(MBB, MBBI, AVR::STSKRr);
 
   switch (MI.getOperand(0).getType()) {
   case MachineOperand::MO_GlobalAddress: {
     const GlobalValue *GV = MI.getOperand(0).getGlobal();
     int64_t Offs = MI.getOperand(0).getOffset();
     unsigned TF = MI.getOperand(0).getTargetFlags();
 
-    MIBLO.addGlobalAddress(GV, Offs, TF);
-    MIBHI.addGlobalAddress(GV, Offs + 1, TF);
+    if (STI.hasLowByteFirst()) {
+      // Write the low byte first for XMEGA devices.
+      MIB0.addGlobalAddress(GV, Offs, TF);
+      MIB1.addGlobalAddress(GV, Offs + 1, TF);
+    } else {
+      // Write the high byte first for traditional devices.
+      MIB0.addGlobalAddress(GV, Offs + 1, TF);
+      MIB1.addGlobalAddress(GV, Offs, TF);
+    }
+
     break;
   }
   case MachineOperand::MO_Immediate: {
     unsigned Imm = MI.getOperand(0).getImm();
 
-    MIBLO.addImm(Imm);
-    MIBHI.addImm(Imm + 1);
+    if (STI.hasLowByteFirst()) {
+      // Write the low byte first for XMEGA devices.
+      MIB0.addImm(Imm);
+      MIB1.addImm(Imm + 1);
+    } else {
+      // Write the high byte first for traditional devices.
+      MIB0.addImm(Imm + 1);
+      MIB1.addImm(Imm);
+    }
+
     break;
   }
   default:
     llvm_unreachable("Unknown operand type!");
   }
 
-  MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
-  MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
-
-  MIBLO.setMemRefs(MI.memoperands());
-  MIBHI.setMemRefs(MI.memoperands());
+  if (STI.hasLowByteFirst()) {
+    // Write the low byte first for XMEGA devices.
+    MIB0.addReg(SrcLoReg, getKillRegState(SrcIsKill))
+        .setMemRefs(MI.memoperands());
+    MIB1.addReg(SrcHiReg, getKillRegState(SrcIsKill))
+        .setMemRefs(MI.memoperands());
+  } else {
+    // Write the high byte first for traditional devices.
+    MIB0.addReg(SrcHiReg, getKillRegState(SrcIsKill))
+        .setMemRefs(MI.memoperands());
+    MIB1.addReg(SrcLoReg, getKillRegState(SrcIsKill))
+        .setMemRefs(MI.memoperands());
+  }
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
buildMI(MBB, MBBI, AVR::STDWPtrQRr)
                 getKillRegState(DstIsKill) | getUndefRegState(DstIsUndef))
         .addImm(0)
         .addReg(SrcReg, getKillRegState(SrcIsKill))
         .setMemRefs(MI.memoperands());
 
   } else {
     Register SrcLoReg, SrcHiReg;
     TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
+    if (STI.hasLowByteFirst()) {
       buildMI(MBB, MBBI, AVR::STPtrRr)
           .addReg(DstReg, getUndefRegState(DstIsUndef))
           .addReg(SrcLoReg, getKillRegState(SrcIsKill))
           .setMemRefs(MI.memoperands());
-
       buildMI(MBB, MBBI, AVR::STDPtrQRr)
           .addReg(DstReg, getUndefRegState(DstIsUndef))
           .addImm(1)
           .addReg(SrcHiReg, getKillRegState(SrcIsKill))
           .setMemRefs(MI.memoperands());
+    } else {
+      buildMI(MBB, MBBI, AVR::STDPtrQRr)
+          .addReg(DstReg, getUndefRegState(DstIsUndef))
+          .addImm(1)
+          .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+          .setMemRefs(MI.memoperands());
+      buildMI(MBB, MBBI, AVR::STPtrRr)
+          .addReg(DstReg, getUndefRegState(DstIsUndef))
+          .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+          .setMemRefs(MI.memoperands());
+    }
   }
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
if (Imm >= 63 || STI.hasTinyEncoding()) {
     // offset (with 2 added after the postincrement instructions) so it is the
     // same as before.
     if (!DstIsKill) {
       buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
           .addReg(DstReg, RegState::Kill)
           .addImm(Imm + 2);
     }
   } else {
-    unsigned OpLo = AVR::STDPtrQRr;
-    unsigned OpHi = AVR::STDPtrQRr;
     Register SrcLoReg, SrcHiReg;
     TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
-    auto MIBLO = buildMI(MBB, MBBI, OpLo)
-                     .addReg(DstReg)
-                     .addImm(Imm)
-                     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
-
-    auto MIBHI = buildMI(MBB, MBBI, OpHi)
-                     .addReg(DstReg, getKillRegState(DstIsKill))
-                     .addImm(Imm + 1)
-                     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
-
-    MIBLO.setMemRefs(MI.memoperands());
-    MIBHI.setMemRefs(MI.memoperands());
+    if (STI.hasLowByteFirst()) {
+      buildMI(MBB, MBBI, AVR::STDPtrQRr)
+          .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+          .setMemRefs(MI.memoperands());
+      buildMI(MBB, MBBI, AVR::STDPtrQRr)
+          .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+          .setMemRefs(MI.memoperands());
+    } else {
+      buildMI(MBB, MBBI, AVR::STDPtrQRr)
+          .addReg(DstReg)
+          .addImm(Imm + 1)
+          .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+          .setMemRefs(MI.memoperands());
+      buildMI(MBB, MBBI, AVR::STDPtrQRr)
+          .addReg(DstReg, getKillRegState(DstIsKill))
+          .addImm(Imm)
+          .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+          .setMemRefs(MI.memoperands());
+    }
   }
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STDSPQRr>(Block &MBB, BlockIt MBBI) {
bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
   MIBHI.setMemRefs(MI.memoperands());
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
   MachineInstr &MI = *MBBI;
   Register SrcLoReg, SrcHiReg;
   unsigned Imm = MI.getOperand(0).getImm();
   Register SrcReg = MI.getOperand(1).getReg();
   bool SrcIsKill = MI.getOperand(1).isKill();
-  unsigned OpLo = AVR::OUTARr;
-  unsigned OpHi = AVR::OUTARr;
   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
   // Since we add 1 to the Imm value for the high byte below, and 63 is the
   // highest Imm value allowed for the instruction, 62 is the limit here.
   assert(Imm <= 62 && "Address is out of range");
 
-  // 16 bit I/O writes need the high byte first
-  auto MIBHI = buildMI(MBB, MBBI, OpHi)
-                   .addImm(Imm + 1)
-                   .addReg(SrcHiReg, getKillRegState(SrcIsKill));
-
-  auto MIBLO = buildMI(MBB, MBBI, OpLo)
-                   .addImm(Imm)
-                   .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+  // 16 bit I/O writes need the high byte first on normal AVR devices,
+  // and in reverse order for the XMEGA/XMEGA3/XMEGAU families.
+  auto MIBHI = buildMI(MBB, MBBI, AVR::OUTARr)
+                   .addImm(STI.hasLowByteFirst() ? Imm : Imm + 1)
+                   .addReg(STI.hasLowByteFirst() ? SrcLoReg : SrcHiReg,
+                           getKillRegState(SrcIsKill));
+  auto MIBLO = buildMI(MBB, MBBI, AVR::OUTARr)
+                   .addImm(STI.hasLowByteFirst() ? Imm + 1 : Imm)
+                   .addReg(STI.hasLowByteFirst() ? SrcHiReg : SrcLoReg,
+                           getKillRegState(SrcIsKill));
 
   MIBLO.setMemRefs(MI.memoperands());
   MIBHI.setMemRefs(MI.memoperands());
 
   MI.eraseFromParent();
   return true;
 }
 

llvm/lib/Target/AVR/AVRISelLowering.cpp

bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
   SDLoc DL(N);
 
   if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
     VT = LD->getMemoryVT();
     if (LD->getExtensionType() != ISD::NON_EXTLOAD)
       return false;
   } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
     VT = ST->getMemoryVT();
-    if (AVR::isProgramMemoryAccess(ST)) {
+    // We can not store to program memory.
+    if (AVR::isProgramMemoryAccess(ST))
+      return false;
+    // Since the high byte need to be stored first, we can not emit
+    // i16 post increment store like:
+    // st X+, r24
+    // st X+, r25
+    if (VT == MVT::i16 && !Subtarget.hasLowByteFirst())
       return false;
-    }
   } else {
     return false;
   }
 
   if (VT != MVT::i8 && VT != MVT::i16) {
     return false;
   }
 

llvm/lib/Target/AVR/AVRSubtarget.h

public:
   bool hasSPM() const { return m_hasSPM; }
   bool hasSPMX() const { return m_hasSPMX; }
   bool hasDES() const { return m_hasDES; }
   bool supportsRMW() const { return m_supportsRMW; }
   bool supportsMultiplication() const { return m_supportsMultiplication; }
   bool hasBREAK() const { return m_hasBREAK; }
   bool hasTinyEncoding() const { return m_hasTinyEncoding; }
   bool hasMemMappedGPR() const { return m_hasMemMappedGPR; }
+  bool hasLowByteFirst() const { return m_hasLowByteFirst; }
 
   uint8_t getIORegisterOffset() const { return hasMemMappedGPR() ? 0x20 : 0x0; }
 
   /// Gets the ELF architecture for the e_flags field
   /// of an ELF object file.
   unsigned getELFArch() const {
     assert(ELFArch != 0 &&
            "every device must have an associate ELF architecture");
private:
   bool m_hasELPMX = false;
   bool m_hasSPM = false;
   bool m_hasSPMX = false;
   bool m_hasDES = false;
   bool m_supportsRMW = false;
   bool m_supportsMultiplication = false;
   bool m_hasBREAK = false;
   bool m_hasTinyEncoding = false;
+  bool m_hasLowByteFirst = false;
   bool m_hasMemMappedGPR = false;
 
   // Dummy member, used by FeatureSet's. We cannot have a SubtargetFeature with
   // no variable, so we instead bind pseudo features to this variable.
   bool m_FeatureSetDummy = false;
 
   AVRInstrInfo InstrInfo;
   AVRFrameLowering FrameLowering;
   AVRTargetLowering TLInfo;
   AVRSelectionDAGInfo TSInfo;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_SUBTARGET_H

llvm/test/CodeGen/AVR/PR37143.ll

 ; RUN: llc -mattr=avr6,sram < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK: ld {{r[0-9]+}}, [[PTR:[XYZ]]]
 ; CHECK: ldd {{r[0-9]+}}, [[PTR]]+1
-; CHECK: st [[PTR2:[XYZ]]], {{r[0-9]+}}
-; CHECK: std [[PTR2]]+1, {{r[0-9]+}}
+; CHECK: std [[PTR2:[XYZ]]]+1, {{r[0-9]+}}
+; CHECK: st [[PTR2]], {{r[0-9]+}}
 define void @load_store_16(i16* nocapture %ptr) local_unnamed_addr #1 {
 entry:
   %0 = load i16, i16* %ptr, align 2
   %add = add i16 %0, 5
   store i16 %add, i16* %ptr, align 2
   ret void
 }

llvm/test/CodeGen/AVR/alloca.ll

; CHECK: sbci r23, 255
   ret i16 %call
 }
 
 ; Test writing to an allocated variable with a small and a big offset
 define i16 @alloca_write(i16 %x) {
 entry:
 ; CHECK-LABEL: alloca_write:
 ; Small offset here
-; CHECK: std Y+23, {{.*}}
 ; CHECK: std Y+24, {{.*}}
+; CHECK: std Y+23, {{.*}}
 ; Big offset here
 ; CHECK: adiw r28, 57
-; CHECK: std Y+62, {{.*}}
 ; CHECK: std Y+63, {{.*}}
+; CHECK: std Y+62, {{.*}}
 ; CHECK: sbiw r28, 57
   %p = alloca [15 x i16]
   %k = alloca [14 x i16]
   %arrayidx = getelementptr inbounds [15 x i16], [15 x i16]* %p, i16 0, i16 45
   store i16 22, i16* %arrayidx
   %arrayidx1 = getelementptr inbounds [14 x i16], [14 x i16]* %k, i16 0, i16 11
   store i16 42, i16* %arrayidx1
   %arrayidx2 = getelementptr inbounds [14 x i16], [14 x i16]* %k, i16 0, i16 0
   %arrayidx3 = getelementptr inbounds [15 x i16], [15 x i16]* %p, i16 0, i16 0
   %call = call i16 @allocate(i16* %arrayidx2, i16* %arrayidx3)
   ret i16 %call
 }
 
 ; Test writing to an allocated variable with a huge offset that cant be
 ; materialized with adiw/sbiw but with a subi/sbci pair.
 define void @alloca_write_huge() {
 ; CHECK-LABEL: alloca_write_huge:
 ; CHECK: subi r28, 41
 ; CHECK: sbci r29, 255
-; CHECK: std Y+62, {{.*}}
 ; CHECK: std Y+63, {{.*}}
+; CHECK: std Y+62, {{.*}}
 ; CHECK: subi r28, 215
 ; CHECK: sbci r29, 0
   %k = alloca [140 x i16]
   %arrayidx = getelementptr inbounds [140 x i16], [140 x i16]* %k, i16 0, i16 138
   store i16 22, i16* %arrayidx
   %arraydecay = getelementptr inbounds [140 x i16], [140 x i16]* %k, i16 0, i16 0
   call i16 @allocate(i16* %arraydecay, i16* null)
   ret void
 }

llvm/test/CodeGen/AVR/atomics/load16.ll

 
 ; CHECK-LABEL: atomic_load_add16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
 ; CHECK-NEXT: add [[RR1L:r[0-9]+]], [[RDL]]
 ; CHECK-NEXT: adc [[RR1H:r[0-9]+]], [[RDH]]
-; CHECK-NEXT: st [[RR]], [[RR1L]]
 ; CHECK-NEXT: std [[RR]]+1, [[RR1H]]
+; CHECK-NEXT: st [[RR]], [[RR1L]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_add16(i16* %foo) {
   %val = atomicrmw add i16* %foo, i16 13 seq_cst
   ret i16 %val
 }
 
 ; CHECK-LABEL: atomic_load_sub16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
 ; CHECK-NEXT: movw [[TMPL:r[0-9]+]], [[RDL]]
 ; CHECK-NEXT: sub [[TMPL]],         [[RR1L:r[0-9]+]]
 ; CHECK-NEXT: sbc [[TMPH:r[0-9]+]], [[RR1H:r[0-9]+]]
-; CHECK-NEXT: st [[RR]], [[TMPL]]
 ; CHECK-NEXT: std [[RR]]+1, [[TMPH]]
+; CHECK-NEXT: st [[RR]], [[TMPL]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_sub16(i16* %foo) {
   %val = atomicrmw sub i16* %foo, i16 13 seq_cst
   ret i16 %val
 }
 
 ; CHECK-LABEL: atomic_load_and16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
 ; CHECK-NEXT: and [[RD1L:r[0-9]+]], [[RDL]]
 ; CHECK-NEXT: and [[RD1H:r[0-9]+]], [[RDH]]
-; CHECK-NEXT: st [[RR]], [[RD1L]]
 ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
+; CHECK-NEXT: st [[RR]], [[RD1L]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_and16(i16* %foo) {
   %val = atomicrmw and i16* %foo, i16 13 seq_cst
   ret i16 %val
 }
 
 ; CHECK-LABEL: atomic_load_or16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
 ; CHECK-NEXT: or [[RD1L:r[0-9]+]], [[RDL]]
 ; CHECK-NEXT: or [[RD1H:r[0-9]+]], [[RDH]]
-; CHECK-NEXT: st [[RR]], [[RD1L]]
 ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
+; CHECK-NEXT: st [[RR]], [[RD1L]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_or16(i16* %foo) {
   %val = atomicrmw or i16* %foo, i16 13 seq_cst
   ret i16 %val
 }
 
 ; CHECK-LABEL: atomic_load_xor16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
 ; CHECK-NEXT: eor [[RD1L:r[0-9]+]], [[RDL]]
 ; CHECK-NEXT: eor [[RD1H:r[0-9]+]], [[RDH]]
-; CHECK-NEXT: st [[RR]], [[RD1L]]
 ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
+; CHECK-NEXT: st [[RR]], [[RD1L]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_xor16(i16* %foo) {
   %val = atomicrmw xor i16* %foo, i16 13 seq_cst
   ret i16 %val
 }
 
 ; CHECK-LABEL: atomic_load_nand16
 ; CHECK: call __sync_fetch_and_nand_2

llvm/test/CodeGen/AVR/atomics/store.ll

 ; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
 
 ; CHECK-LABEL: atomic_store8
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
 ; CHECK-NEXT: out 63, r0
 define void @atomic_store8(i8* %foo) {
   store atomic i8 1, i8* %foo unordered, align 1
   ret void
 }
 
 ; CHECK-LABEL: atomic_store16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
-; CHECK-NEXT: std [[RD]]+1, [[RR:r[0-9]+]]
+; CHECK-NEXT: std [[RD:(X|Y|Z)]]+1, [[RR:r[0-9]+]]
+; CHECK-NEXT: st [[RD]], [[RR:r[0-9]+]]
 ; CHECK-NEXT: out 63, r0
 define void @atomic_store16(i16* %foo) {
   store atomic i16 1, i16* %foo unordered, align 2
   ret void
 }
 
 ; CHECK-LABEL: atomic_store32
 ; CHECK: call __sync_lock_test_and_set_4

llvm/test/CodeGen/AVR/atomics/store16.ll

 ; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
 
 ; CHECK-LABEL: atomic_store16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
 ; CHECK-NEXT: std [[RD:(X|Y|Z)]]+1, [[RR:r[0-9]+]]
+; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
 ; CHECK-NEXT: out 63, r0
 define void @atomic_store16(i16* %foo) {
   store atomic i16 1, i16* %foo unordered, align 2
   ret void
 }
 
 ; CHECK-LABEL: monotonic
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: st Z, r24
 ; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
 ; CHECK-NEXT: out 63, r0
 define void @monotonic(i16) {
 entry-block:
   store atomic i16 %0, i16* undef monotonic, align 2
   ret void
 }
 

llvm/test/CodeGen/AVR/call.ll

; AVR2:  rcall foo8_2
     %result2 = call i8 @foo8_2(i8 12, i8 13, i8 14)
     ret i8 %result2
 }
 
 define i8 @calli8_stack() {
 ; CHECK-LABEL: calli8_stack:
 ; CHECK: ldi [[REG1:r[0-9]+]], 10
 ; CHECK: ldi [[REG2:r[0-9]+]], 11
-; CHECK: std Z+1, [[REG1]]
 ; CHECK: std Z+2, [[REG2]]
+; CHECK: std Z+1, [[REG1]]
 ; AVR6:  call foo8_3
 ; AVR2:  rcall foo8_3
     %result1 = call i8 @foo8_3(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11)
     ret i8 %result1
 }
 
 define i16 @calli16_reg() {
 ; CHECK-LABEL: calli16_reg:
 ; CHECK: ldi r24, 1
 ; CHECK: ldi r25, 2
 ; CHECK: ldi r22, 2
 ; CHECK: ldi r23, 2
 ; AVR6:  call foo16_1
 ; AVR2:  rcall foo16_1
     %result1 = call i16 @foo16_1(i16 513, i16 514)
     ret i16 %result1
 }
 
 define i16 @calli16_stack() {
 ; CHECK-LABEL: calli16_stack:
 ; CHECK: ldi [[REG1:r[0-9]+]], 10
 ; CHECK: ldi [[REG2:r[0-9]+]], 2
-; CHECK: std Z+3, [[REG1]]
 ; CHECK: std Z+4, [[REG2]]
+; CHECK: std Z+3, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 9
 ; CHECK: ldi [[REG2:r[0-9]+]], 2
-; CHECK: std Z+1, [[REG1]]
 ; CHECK: std Z+2, [[REG2]]
+; CHECK: std Z+1, [[REG1]]
 ; AVR6:  call foo16_2
 ; AVR2:  rcall foo16_2
     %result1 = call i16 @foo16_2(i16 512, i16 513, i16 514, i16 515, i16 516, i16 517, i16 518, i16 519, i16 520, i16 521, i16 522)
     ret i16 %result1
 }
 
 define i32 @calli32_reg() {
 ; CHECK-LABEL: calli32_reg:
; AVR2:  rcall foo32_1
     %result1 = call i32 @foo32_1(i32 34554432, i32 35554432)
     ret i32 %result1
 }
 
 define i32 @calli32_stack() {
 ; CHECK-LABEL: calli32_stack:
 ; CHECK: ldi [[REG1:r[0-9]+]], 15
 ; CHECK: ldi [[REG2:r[0-9]+]], 2
-; CHECK: std Z+3, [[REG1]]
 ; CHECK: std Z+4, [[REG2]]
+; CHECK: std Z+3, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 64
 ; CHECK: ldi [[REG2:r[0-9]+]], 66
-; CHECK: std Z+1, [[REG1]]
 ; CHECK: std Z+2, [[REG2]]
+; CHECK: std Z+1, [[REG1]]
 ; AVR6:  call foo32_2
 ; AVR2:  rcall foo32_2
     %result1 = call i32 @foo32_2(i32 1, i32 2, i32 3, i32 4, i32 34554432)
     ret i32 %result1
 }
 
 define i64 @calli64_reg() {
 ; CHECK-LABEL: calli64_reg:
; AVR2:  rcall foo64_1
     ret i64 %result1
 }
 
 define i64 @calli64_stack() {
 ; CHECK-LABEL: calli64_stack:
 
 ; CHECK: ldi [[REG1:r[0-9]+]], 31
 ; CHECK: ldi [[REG2:r[0-9]+]], 242
-; CHECK: std Z+7, [[REG1]]
 ; CHECK: std Z+8, [[REG2]]
+; CHECK: std Z+7, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 76
 ; CHECK: ldi [[REG2:r[0-9]+]], 73
-; CHECK: std Z+5, [[REG1]]
 ; CHECK: std Z+6, [[REG2]]
+; CHECK: std Z+5, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 155
 ; CHECK: ldi [[REG2:r[0-9]+]], 88
-; CHECK: std Z+3, [[REG1]]
 ; CHECK: std Z+4, [[REG2]]
+; CHECK: std Z+3, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 255
 ; CHECK: ldi [[REG2:r[0-9]+]], 255
-; CHECK: std Z+1, [[REG1]]
 ; CHECK: std Z+2, [[REG2]]
+; CHECK: std Z+1, [[REG1]]
 ; AVR6:  call foo64_2
 ; AVR2:  rcall foo64_2
     %result1 = call i64 @foo64_2(i64 1, i64 2, i64 17446744073709551615)
     ret i64 %result1
 }
 
 ; Test passing arguments through the stack when the call frame is allocated
 ; in the prologue.
 declare void @foo64_3(i64, i64, i64, i8, i16*)
 
 define void @testcallprologue() {
 ; CHECK-LABEL: testcallprologue:
 ; CHECK: push r28
 ; CHECK: push r29
 ; CHECK: sbiw r28, 27
 ; CHECK: ldi [[REG1:r[0-9]+]], 88
 ; CHECK: std Y+9, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 11
 ; CHECK: ldi [[REG2:r[0-9]+]], 10
-; CHECK: std Y+7, [[REG1]]
 ; CHECK: std Y+8, [[REG2]]
+; CHECK: std Y+7, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 13
 ; CHECK: ldi [[REG2:r[0-9]+]], 12
-; CHECK: std Y+5, [[REG1]]
 ; CHECK: std Y+6, [[REG2]]
+; CHECK: std Y+5, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 15
 ; CHECK: ldi [[REG2:r[0-9]+]], 14
-; CHECK: std Y+3, [[REG1]]
 ; CHECK: std Y+4, [[REG2]]
+; CHECK: std Y+3, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 8
 ; CHECK: ldi [[REG2:r[0-9]+]], 9
-; CHECK: std Y+1, [[REG1]]
 ; CHECK: std Y+2, [[REG2]]
+; CHECK: std Y+1, [[REG1]]
 ; CHECK: pop r29
 ; CHECK: pop r28
   %p = alloca [8 x i16]
   %arraydecay = getelementptr inbounds [8 x i16], [8 x i16]* %p, i16 0, i16 0
   call void @foo64_3(i64 723685415333071112, i64 723685415333071112, i64 723685415333071112, i8 88, i16* %arraydecay)
   ret void
 }
 

llvm/test/CodeGen/AVR/dynalloca.ll

 ; CHECK: sub
 ; CHECK: sbc
 ; CHECK: in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: out 62, {{.*}}
 ; CHECK-NEXT: out 63, r0
 ; CHECK-NEXT: out 61, {{.*}}
 ; Test writes
-; CHECK: std Z+12, {{.*}}
 ; CHECK: std Z+13, {{.*}}
+; CHECK: std Z+12, {{.*}}
 ; CHECK: std Z+7, {{.*}}
 ; CHECK-NOT: std
 ; Test SP restore
 ; CHECK: in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: out 62, r29
 ; CHECK-NEXT: out 63, r0
 ; CHECK-NEXT: out 61, r28

 ; CHECK: in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: out 62, {{.*}}
 ; CHECK-NEXT: out 63, r0
 ; CHECK-NEXT: out 61, {{.*}}
 ; Store values on the stack
 ; CHECK: ldi r16, 0
 ; CHECK: ldi r17, 0
-; CHECK: std Z+7, r16
 ; CHECK: std Z+8, r17
-; CHECK: std Z+5, r16
+; CHECK: std Z+7, r16
 ; CHECK: std Z+6, r17
-; CHECK: std Z+3, r16
+; CHECK: std Z+5, r16
 ; CHECK: std Z+4, r17
-; CHECK: std Z+1, r16
+; CHECK: std Z+3, r16
 ; CHECK: std Z+2, r17
+; CHECK: std Z+1, r16
 ; CHECK: call
 ; Call frame restore
 ; CHECK-NEXT: in r30, 61
 ; CHECK-NEXT: in r31, 62
 ; CHECK-NEXT: adiw r30, 8
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: out 62, r31

llvm/test/CodeGen/AVR/lpmx.ll

 ; CHECK-O0-NEXT:    in r28, 61
 ; CHECK-O0-NEXT:    in r29, 62
 ; CHECK-O0-NEXT:    sbiw r28, 2
 ; CHECK-O0-NEXT:    in r0, 63
 ; CHECK-O0-NEXT:    cli
 ; CHECK-O0-NEXT:    out 62, r29
 ; CHECK-O0-NEXT:    out 63, r0
 ; CHECK-O0-NEXT:    out 61, r28
-; CHECK-O0-NEXT:    std Y+1, r24
 ; CHECK-O0-NEXT:    std Y+2, r25
+; CHECK-O0-NEXT:    std Y+1, r24
 ; CHECK-O0-NEXT:    ldd r30, Y+1
 ; CHECK-O0-NEXT:    ldd r31, Y+2
 ; CHECK-O0-NEXT:    lsl r30
 ; CHECK-O0-NEXT:    rol r31
 ; CHECK-O0-NEXT:    subi r30, lo8(-(arr0))
 ; CHECK-O0-NEXT:    sbci r31, hi8(-(arr0))
 ; CHECK-O0-NEXT:    lpm r24, Z+
 ; CHECK-O0-NEXT:    lpm r25, Z

 ; CHECK-O3-NEXT:    in r28, 61
 ; CHECK-O3-NEXT:    in r29, 62
 ; CHECK-O3-NEXT:    sbiw r28, 2
 ; CHECK-O3-NEXT:    in r0, 63
 ; CHECK-O3-NEXT:    cli
 ; CHECK-O3-NEXT:    out 62, r29
 ; CHECK-O3-NEXT:    out 63, r0
 ; CHECK-O3-NEXT:    out 61, r28
-; CHECK-O3-NEXT:    std Y+1, r24
 ; CHECK-O3-NEXT:    std Y+2, r25
+; CHECK-O3-NEXT:    std Y+1, r24
 ; CHECK-O3-NEXT:    lsl r24
 ; CHECK-O3-NEXT:    rol r25
 ; CHECK-O3-NEXT:    subi r24, lo8(-(arr0))
 ; CHECK-O3-NEXT:    sbci r25, hi8(-(arr0))
 ; CHECK-O3-NEXT:    movw r30, r24
 ; CHECK-O3-NEXT:    lpm r24, Z+
 ; CHECK-O3-NEXT:    lpm r25, Z
 ; CHECK-O3-NEXT:    adiw r28, 2

 ; CHECK-O0-NEXT:    in r28, 61
 ; CHECK-O0-NEXT:    in r29, 62
 ; CHECK-O0-NEXT:    sbiw r28, 2
 ; CHECK-O0-NEXT:    in r0, 63
 ; CHECK-O0-NEXT:    cli
 ; CHECK-O0-NEXT:    out 62, r29
 ; CHECK-O0-NEXT:    out 63, r0
 ; CHECK-O0-NEXT:    out 61, r28
-; CHECK-O0-NEXT:    std Y+1, r24
 ; CHECK-O0-NEXT:    std Y+2, r25
+; CHECK-O0-NEXT:    std Y+1, r24
 ; CHECK-O0-NEXT:    ldd r30, Y+1
 ; CHECK-O0-NEXT:    ldd r31, Y+2
 ; CHECK-O0-NEXT:    subi r30, lo8(-(arr1))
 ; CHECK-O0-NEXT:    sbci r31, hi8(-(arr1))
 ; CHECK-O0-NEXT:    lpm r24, Z
 ; CHECK-O0-NEXT:    adiw r28, 2
 ; CHECK-O0-NEXT:    in r0, 63
 ; CHECK-O0-NEXT:    cli

 ; CHECK-O3-NEXT:    in r28, 61
 ; CHECK-O3-NEXT:    in r29, 62
 ; CHECK-O3-NEXT:    sbiw r28, 2
 ; CHECK-O3-NEXT:    in r0, 63
 ; CHECK-O3-NEXT:    cli
 ; CHECK-O3-NEXT:    out 62, r29
 ; CHECK-O3-NEXT:    out 63, r0
 ; CHECK-O3-NEXT:    out 61, r28
-; CHECK-O3-NEXT:    std Y+1, r24
 ; CHECK-O3-NEXT:    std Y+2, r25
+; CHECK-O3-NEXT:    std Y+1, r24
 ; CHECK-O3-NEXT:    subi r24, lo8(-(arr1))
 ; CHECK-O3-NEXT:    sbci r25, hi8(-(arr1))
 ; CHECK-O3-NEXT:    movw r30, r24
 ; CHECK-O3-NEXT:    lpm r24, Z
 ; CHECK-O3-NEXT:    adiw r28, 2
 ; CHECK-O3-NEXT:    in r0, 63
 ; CHECK-O3-NEXT:    cli
 ; CHECK-O3-NEXT:    out 62, r29

llvm/test/CodeGen/AVR/pr43443-ctor-alias.ll

 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
 ; CHECK-NEXT:    sbiw r28, 2
 ; CHECK-NEXT:    in r0, 63
 ; CHECK-NEXT:    cli
 ; CHECK-NEXT:    out 62, r29
 ; CHECK-NEXT:    out 63, r0
 ; CHECK-NEXT:    out 61, r28
-; CHECK-NEXT:    std Y+1, r24
 ; CHECK-NEXT:    std Y+2, r25
+; CHECK-NEXT:    std Y+1, r24
 ; CHECK-NEXT:    adiw r28, 2
 ; CHECK-NEXT:    in r0, 63
 ; CHECK-NEXT:    cli
 ; CHECK-NEXT:    out 62, r29
 ; CHECK-NEXT:    out 63, r0
 ; CHECK-NEXT:    out 61, r28
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28

llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir

-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mtriple=avr -mcpu=attiny11 %s -o - \
+# RUN:     | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mtriple=avr -mcpu=atmega328 %s -o - \
+# RUN:     | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mtriple=avr -mcpu=attiny817 %s -o - \
+# RUN:     | FileCheck --check-prefix=XMEGA %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mtriple=avr -mcpu=atxmega64a1 %s -o - \
+# RUN:     | FileCheck --check-prefix=XMEGA %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mtriple=avr -mcpu=atxmega256a3u %s -o - \
+# RUN:     | FileCheck --check-prefix=XMEGA %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
     liveins: $r15r14
 
     ; CHECK-LABEL: test
-
-    ; CHECK:      OUTARr 32, $r15
-    ; CHECK-NEXT: OUTARr 31, $r14
+    ; CHECK:       OUTARr 32, $r15
+    ; CHECK-NEXT:  OUTARr 31, $r14
 
+    ; XMEGA-LABEL: test
+    ; XMEGA:       OUTARr 31, $r14
+    ; XMEGA-NEXT:  OUTARr 32, $r15
+
     OUTWARr 31, $r15r14
 ...

llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs -mattr=avrtiny %s -o - | FileCheck %s --check-prefix=CHECK-TINY
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs -mattr=avrtiny %s -o - \
+# RUN:     | FileCheck %s --check-prefix=CHECK-TINY
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs -mattr=lowbytefirst %s -o - \
+# RUN:     | FileCheck %s --check-prefix=CHECK-XMEGA
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
 
     ; CHECK-LABEL: test
 
     ; Small displacement (<63):
-    ; CHECK:      STDPtrQRr $r29r28, 3, $r0
-    ; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
-    ; CHECK-TINY:      $r28 = SUBIRdK killed $r28, 253, implicit-def $sreg
-    ; CHECK-TINY-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
-    ; CHECK-TINY-NEXT: early-clobber $r29r28 = STPtrPiRr killed $r29r28, $r0, 0
-    ; CHECK-TINY-NEXT: early-clobber $r29r28 = STPtrPiRr killed $r29r28, $r1, 0
-    ; CHECK-TINY-NEXT: $r28 = SUBIRdK killed $r28, 5, implicit-def $sreg
-    ; CHECK-TINY-NEXT: $r29 = SBCIRdK killed $r29, 0, implicit-def $sreg, implicit killed $sreg
+    ; CHECK:            STDPtrQRr $r29r28, 4, $r1
+    ; CHECK-NEXT:       STDPtrQRr $r29r28, 3, $r0
+    ; CHECK-XMEGA:      STDPtrQRr $r29r28, 3, $r0
+    ; CHECK-XMEGA-NEXT: STDPtrQRr $r29r28, 4, $r1
+    ; CHECK-TINY:       $r28 = SUBIRdK killed $r28, 253, implicit-def $sreg
+    ; CHECK-TINY-NEXT:  $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-TINY-NEXT:  early-clobber $r29r28 = STPtrPiRr killed $r29r28, $r0, 0
+    ; CHECK-TINY-NEXT:  early-clobber $r29r28 = STPtrPiRr killed $r29r28, $r1, 0
+    ; CHECK-TINY-NEXT:  $r28 = SUBIRdK killed $r28, 5, implicit-def $sreg
+    ; CHECK-TINY-NEXT:  $r29 = SBCIRdK killed $r29, 0, implicit-def $sreg, implicit killed $sreg
     STDWPtrQRr $r29r28, 3, $r1r0
 
     ; Small displacement where the destination register is killed:
-    ; CHECK:      STDPtrQRr $r29r28, 3, $r0
-    ; CHECK-NEXT: STDPtrQRr killed $r29r28, 4, $r1
+    ; CHECK-NEXT:       STDPtrQRr $r29r28, 4, $r1
+    ; CHECK-NEXT:       STDPtrQRr killed $r29r28, 3, $r0
+    ; CHECK-XMEGA-NEXT: STDPtrQRr $r29r28, 3, $r0
+    ; CHECK-XMEGA-NEXT: STDPtrQRr killed $r29r28, 4, $r1
     STDWPtrQRr killed $r29r28, 3, $r1r0
 
     ; Small displacement where the source register is killed:
-    ; CHECK:      STDPtrQRr $r29r28, 3, killed $r0
-    ; CHECK-NEXT: STDPtrQRr $r29r28, 4, killed $r1
+    ; CHECK:            STDPtrQRr $r29r28, 4, killed $r1
+    ; CHECK-NEXT:       STDPtrQRr $r29r28, 3, killed $r0
+    ; CHECK-XMEGA:      STDPtrQRr $r29r28, 3, killed $r0
+    ; CHECK-XMEGA-NEXT: STDPtrQRr $r29r28, 4, killed $r1
     STDWPtrQRr $r29r28, 3, killed $r1r0
 
     ; Small displacement, near the limit (=62):
-    ; CHECK:      STDPtrQRr $r29r28, 62, $r0
-    ; CHECK-NEXT: STDPtrQRr $r29r28, 63, $r1
+    ; CHECK:            STDPtrQRr $r29r28, 63, $r1
+    ; CHECK-NEXT:       STDPtrQRr $r29r28, 62, $r0
+    ; CHECK-XMEGA:      STDPtrQRr $r29r28, 62, $r0
+    ; CHECK-XMEGA-NEXT: STDPtrQRr $r29r28, 63, $r1
     STDWPtrQRr $r29r28, 62, $r1r0
 
     ; Large displacement (>=63):
     ; CHECK:      $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
     ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
     ; CHECK-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r0, 0
     ; CHECK-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r1, 0
     ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 65, implicit-def $sreg

llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mcpu=atxmega64a1 %s -o - \
+# RUN:     | FileCheck --check-prefix=XMEGA %s
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_stswkrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_stswkrr
 body: |
   bb.0.entry:
     liveins: $r31r30
 
     ; CHECK-LABEL: test_stswkrr
-
-    ; CHECK:      STSKRr 2560, $r31
-    ; CHECK-NEXT: STSKRr 2559, $r30
+    ; CHECK:       STSKRr 2560, $r31
+    ; CHECK-NEXT:  STSKRr 2559, $r30
 
+    ; XMEGA-LABEL: test_stswkrr
+    ; XMEGA:       STSKRr 2559, $r30
+    ; XMEGA-NEXT:  STSKRr 2560, $r31
+
     STSWKRr 2559, $r31r30
 ...

llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
-# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=avrtiny %s -o - | FileCheck %s --check-prefix=CHECK-TINY
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=avrtiny %s -o - \
+# RUN:     | FileCheck %s --check-prefix=CHECK-TINY
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=lowbytefirst %s -o - \
+# RUN:     | FileCheck %s --check-prefix=CHECK-XMEGA
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_stwptrrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_stwptrrr
 body: |
   bb.0.entry:
     liveins: $r31r30, $r17r16
 
     ; CHECK-LABEL: test_stwptrrr
+    ; CHECK:       STDPtrQRr $r31r30, 1, $r17
+    ; CHECK-NEXT:  STPtrRr $r31r30, $r16
 
-    ; CHECK:      STPtrRr $r31r30, $r16
-    ; CHECK-NEXT: STDPtrQRr $r31r30, 1, $r17
-
-    ; CHECK-TINY:      $r31r30 = STPtrPiRr killed $r31r30, $r16, 0
-    ; CHECK-TINY-NEXT: $r31r30 = STPtrPiRr killed $r31r30, $r17, 0
-    ; CHECK-TINY-NEXT: $r30 = SUBIRdK killed $r30, 2, implicit-def $sreg
-    ; CHECK-TINY-NEXT: $r31 = SBCIRdK killed $r31, 0, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-TINY-LABEL: test_stwptrrr
+    ; CHECK-TINY:       $r31r30 = STPtrPiRr killed $r31r30, $r16, 0
+    ; CHECK-TINY-NEXT:  $r31r30 = STPtrPiRr killed $r31r30, $r17, 0
+    ; CHECK-TINY-NEXT:  $r30 = SUBIRdK killed $r30, 2, implicit-def $sreg
+    ; CHECK-TINY-NEXT:  $r31 = SBCIRdK killed $r31, 0, implicit-def $sreg, implicit killed $sreg
 
+    ; CHECK-XMEGA-LABEL: test_stwptrrr
+    ; CHECK-XMEGA:       STPtrRr $r31r30, $r16
+    ; CHECK-XMEGA-NEXT:  STDPtrQRr $r31r30, 1, $r17
+
     STWPtrRr $r31r30, $r17r16
 ...

llvm/test/CodeGen/AVR/shift32.ll

 
 ; Combined with the register allocator, shift instructions can sometimes be
 ; optimized away entirely. The least significant registers are simply stored
 ; directly instead of moving them first.
 define void @shl_i32_16_ptr(i32 %a, ptr %ptr) {
 ; CHECK-LABEL: shl_i32_16_ptr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    movw r30, r20
-; CHECK-NEXT:    std Z+2, r22
 ; CHECK-NEXT:    std Z+3, r23
+; CHECK-NEXT:    std Z+2, r22
 ; CHECK-NEXT:    ldi r24, 0
 ; CHECK-NEXT:    ldi r25, 0
-; CHECK-NEXT:    st Z, r24
 ; CHECK-NEXT:    std Z+1, r25
+; CHECK-NEXT:    st Z, r24
 ; CHECK-NEXT:    ret
   %res = shl i32 %a, 16
   store i32 %res, ptr %ptr
   ret void
 }
 
 ; shift only the most significant byte and then move it
 define i32 @shl_i32_28(i32 %a) {

llvm/test/CodeGen/AVR/store.ll

 ; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
 
 define void @store8(i8* %x, i8 %y) {
 ; CHECK-LABEL: store8:
 ; CHECK: st {{[XYZ]}}, r22
   store i8 %y, i8* %x
   ret void
 }
 
 define void @store16(i16* %x, i16 %y) {
 ; CHECK-LABEL: store16:
-; CHECK: st {{[YZ]}}, r22
 ; CHECK: std {{[YZ]}}+1, r23
+; CHECK: st {{[YZ]}}, r22
   store i16 %y, i16* %x
   ret void
 }
 
 define void @store8disp(i8* %x, i8 %y) {
 ; CHECK-LABEL: store8disp:
 ; CHECK: std {{[YZ]}}+63, r22
   %arrayidx = getelementptr inbounds i8, i8* %x, i16 63

 ; CHECK: st {{[XYZ]}}, r22
   %arrayidx = getelementptr inbounds i8, i8* %x, i16 64
   store i8 %y, i8* %arrayidx
   ret void
 }
 
 define void @store16disp(i16* %x, i16 %y) {
 ; CHECK-LABEL: store16disp:
-; CHECK: std {{[YZ]}}+62, r22
 ; CHECK: std {{[YZ]}}+63, r23
+; CHECK: std {{[YZ]}}+62, r22
   %arrayidx = getelementptr inbounds i16, i16* %x, i16 31
   store i16 %y, i16* %arrayidx
   ret void
 }
 
 define void @store16nodisp(i16* %x, i16 %y) {
 ; CHECK-LABEL: store16nodisp:
 ; CHECK: subi r24, 192
 ; CHECK: sbci r25, 255
 ; CHECK: movw r30, r24
-; CHECK: st {{[YZ]}}, r22
 ; CHECK: std {{[YZ]}}+1, r23
+; CHECK: st {{[YZ]}}, r22
   %arrayidx = getelementptr inbounds i16, i16* %x, i16 32
   store i16 %y, i16* %arrayidx
   ret void
 }
 
 define void @store8postinc(i8* %x, i8 %y) {
 ; CHECK-LABEL: store8postinc:
 ; CHECK: st {{[XYZ]}}+, {{.*}}
while.body:                                       ; preds = %entry, %while.body
   %tobool = icmp eq i8 %dec5, 0
   br i1 %tobool, label %while.end, label %while.body
 while.end:                                        ; preds = %while.body, %entry
   ret void
 }
 
 define void @store16postinc(i16* %x, i16 %y) {
 ; CHECK-LABEL: store16postinc:
-; CHECK: st {{[XYZ]}}+, {{.*}}
-; CHECK: st {{[XYZ]}}+, {{.*}}
+; CHECK: std {{[XYZ]}}+1, {{.*}}
+; CHECK: st  {{[XYZ]}}, {{.*}}
 entry:
   %tobool3 = icmp eq i16 %y, 0
   br i1 %tobool3, label %while.end, label %while.body
 while.body:                                       ; preds = %entry, %while.body
   %dec5.in = phi i16 [ %dec5, %while.body ], [ %y, %entry ]
   %x.addr.04 = phi i16* [ %incdec.ptr, %while.body ], [ %x, %entry ]
   %dec5 = add nsw i16 %dec5.in, -1
   %incdec.ptr = getelementptr inbounds i16, i16* %x.addr.04, i16 1

llvm/test/CodeGen/AVR/struct.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=avr < %s | FileCheck %s --check-prefix=CHECKA
 ; RUN: llc -mtriple=avr -mattr=+movw < %s | FileCheck %s --check-prefix=CHECKB
 
 %struct.s10 = type { i16, i16, i16, i16, i16 }
 %struct.s06 = type { i16, i16, i16 }
 %struct.s04 = type { i16, i16 }
 
 define void @foo10(%struct.s10* sret(%struct.s10) %0, i16 %1, i16 %2, i16 %3) addrspace(1) {
 ; CHECKA-LABEL: foo10:
 ; CHECKA:       ; %bb.0:
 ; CHECKA-NEXT:    mov r30, r24
 ; CHECKA-NEXT:    mov r31, r25
-; CHECKA-NEXT:    std Z+4, r22
 ; CHECKA-NEXT:    std Z+5, r23
-; CHECKA-NEXT:    std Z+2, r20
+; CHECKA-NEXT:    std Z+4, r22
 ; CHECKA-NEXT:    std Z+3, r21
-; CHECKA-NEXT:    st Z, r18
+; CHECKA-NEXT:    std Z+2, r20
 ; CHECKA-NEXT:    std Z+1, r19
+; CHECKA-NEXT:    st Z, r18
 ; CHECKA-NEXT:    ret
 ;
 ; CHECKB-LABEL: foo10:
 ; CHECKB:       ; %bb.0:
 ; CHECKB-NEXT:    movw r30, r24
-; CHECKB-NEXT:    std Z+4, r22
 ; CHECKB-NEXT:    std Z+5, r23
-; CHECKB-NEXT:    std Z+2, r20
+; CHECKB-NEXT:    std Z+4, r22
 ; CHECKB-NEXT:    std Z+3, r21
-; CHECKB-NEXT:    st Z, r18
+; CHECKB-NEXT:    std Z+2, r20
 ; CHECKB-NEXT:    std Z+1, r19
+; CHECKB-NEXT:    st Z, r18
 ; CHECKB-NEXT:    ret
   %5 = getelementptr inbounds %struct.s10, %struct.s10* %0, i16 0, i32 0
   store i16 %3, i16* %5
   %6 = getelementptr inbounds %struct.s10, %struct.s10* %0, i16 0, i32 1
   store i16 %2, i16* %6
   %7 = getelementptr inbounds %struct.s10, %struct.s10* %0, i16 0, i32 2
   store i16 %1, i16* %7
   ret void

llvm/test/CodeGen/AVR/varargs.ll

; CHECK: ldd r25, [[REG]]+{{[0-9]+}}
   ret i16 %1
 }
 
 declare void @var1223(i16, ...)
 define void @varargcall() {
 ; CHECK-LABEL: varargcall:
 ; CHECK: ldi [[REG1:r[0-9]+]], 191
 ; CHECK: ldi [[REG2:r[0-9]+]], 223
-; CHECK: std Z+5, [[REG1]]
 ; CHECK: std Z+6, [[REG2]]
+; CHECK: std Z+5, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 189
 ; CHECK: ldi [[REG2:r[0-9]+]], 205
-; CHECK: std Z+3, [[REG1]]
 ; CHECK: std Z+4, [[REG2]]
+; CHECK: std Z+3, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 205
 ; CHECK: ldi [[REG2:r[0-9]+]], 171
-; CHECK: std Z+1, [[REG1]]
 ; CHECK: std Z+2, [[REG2]]
+; CHECK: std Z+1, [[REG1]]
 ; CHECK: call
 ; CHECK: adiw r30, 6
   tail call void (i16, ...) @var1223(i16 -21555, i16 -12867, i16 -8257)
   ret void
 }