[CodeGen] Verify implicit operands in MachineVerifier instead of MIR parser

[foad]

This is work in progress...

Failed Tests (244):
  LLVM :: CodeGen/AArch64/GlobalISel/fold-fp-select.mir
  LLVM :: CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
  LLVM :: CodeGen/AArch64/GlobalISel/select-fp-casts.mir
  LLVM :: CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir
  LLVM :: CodeGen/AArch64/arm64-abi.ll
  LLVM :: CodeGen/AArch64/cfinv-def-nzcv.mir
  LLVM :: CodeGen/AArch64/cfinv-use-nzcv.mir
  LLVM :: CodeGen/AArch64/fjcvtzs.mir
  LLVM :: CodeGen/AArch64/loh.mir
  LLVM :: CodeGen/AArch64/machine-dead-copy.mir
  LLVM :: CodeGen/AArch64/machine-outliner-2fixup-blr-terminator.mir
  LLVM :: CodeGen/AArch64/pr51516.mir
  LLVM :: CodeGen/AArch64/rmif-def-nzcv.mir
  LLVM :: CodeGen/AArch64/rmif-use-nzcv.mir
  LLVM :: CodeGen/AArch64/setf16-def-nzcv.mir
  LLVM :: CodeGen/AArch64/setf16-use-nzcv.mir
  LLVM :: CodeGen/AArch64/setf8-def-nzcv.mir
  LLVM :: CodeGen/AArch64/setf8-use-nzcv.mir
  LLVM :: CodeGen/AArch64/sve-ptest-removal-rdffr.mir
  LLVM :: CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/extractelement.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/insertelement.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/mul.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/sdivrem.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/udivrem.ll
  LLVM :: CodeGen/AMDGPU/add.ll
  LLVM :: CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
  LLVM :: CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
  LLVM :: CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
  LLVM :: CodeGen/AMDGPU/carryout-selection.ll
  LLVM :: CodeGen/AMDGPU/chain-hi-to-lo.ll
  LLVM :: CodeGen/AMDGPU/change-scc-to-vcc.mir
  LLVM :: CodeGen/AMDGPU/combine-add-zext-xor.ll
  LLVM :: CodeGen/AMDGPU/ctlz.ll
  LLVM :: CodeGen/AMDGPU/cttz.ll
  LLVM :: CodeGen/AMDGPU/dpp64_combine.ll
  LLVM :: CodeGen/AMDGPU/ds-sub-offset.ll
  LLVM :: CodeGen/AMDGPU/dual-source-blend-export.ll
  LLVM :: CodeGen/AMDGPU/fdiv.ll
  LLVM :: CodeGen/AMDGPU/flat-offset-bug.ll
  LLVM :: CodeGen/AMDGPU/fmac.sdwa.ll
  LLVM :: CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
  LLVM :: CodeGen/AMDGPU/frem.ll
  LLVM :: CodeGen/AMDGPU/gfx10-vop-literal.ll
  LLVM :: CodeGen/AMDGPU/idiv-licm.ll
  LLVM :: CodeGen/AMDGPU/insert-branch-w32.mir
  LLVM :: CodeGen/AMDGPU/known-never-nan.ll
  LLVM :: CodeGen/AMDGPU/lds-misaligned-bug.ll
  LLVM :: CodeGen/AMDGPU/llvm.amdgcn.exp.ll
  LLVM :: CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
  LLVM :: CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
  LLVM :: CodeGen/AMDGPU/llvm.mulo.ll
  LLVM :: CodeGen/AMDGPU/loop_header_nopred.mir
  LLVM :: CodeGen/AMDGPU/mad_64_32.ll
  LLVM :: CodeGen/AMDGPU/min.ll
  LLVM :: CodeGen/AMDGPU/mul.ll
  LLVM :: CodeGen/AMDGPU/offset-split-flat.ll
  LLVM :: CodeGen/AMDGPU/offset-split-global.ll
  LLVM :: CodeGen/AMDGPU/promote-constOffset-to-imm.ll
  LLVM :: CodeGen/AMDGPU/saddo.ll
  LLVM :: CodeGen/AMDGPU/sdwa-peephole.ll
  LLVM :: CodeGen/AMDGPU/shl_add_ptr_csub.ll
  LLVM :: CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
  LLVM :: CodeGen/AMDGPU/sink-image-sample.ll
  LLVM :: CodeGen/AMDGPU/skip-if-dead.ll
  LLVM :: CodeGen/AMDGPU/smrd.ll
  LLVM :: CodeGen/AMDGPU/uniform-phi-with-undef.ll
  LLVM :: CodeGen/AMDGPU/waitcnt-vscnt.ll
  LLVM :: CodeGen/AMDGPU/wave32.ll
  LLVM :: CodeGen/AMDGPU/wqm.ll
  LLVM :: CodeGen/ARM/GlobalISel/arm-unsupported.ll
  LLVM :: CodeGen/ARM/atomic-cmpxchg.ll
  LLVM :: CodeGen/ARM/atomic-ops-v8.ll
  LLVM :: CodeGen/ARM/cmpxchg-O0.ll
  LLVM :: CodeGen/ARM/coalesce-subregs.ll
  LLVM :: CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
  LLVM :: CodeGen/ARM/intrinsics-overflow.ll
  LLVM :: CodeGen/ARM/ldm-stm-i256.ll
  LLVM :: CodeGen/ARM/machine-outliner-unoutlinable.mir
  LLVM :: CodeGen/ARM/machine-outliner-unsafe-registers.mir
  LLVM :: CodeGen/ARM/unschedule-reg-sequence.ll
  LLVM :: CodeGen/ARM/urem-opt-size.ll
  LLVM :: CodeGen/ARM/wide-compares.ll
  LLVM :: CodeGen/AVR/pseudo/COPY.mir
  LLVM :: CodeGen/Hexagon/anti-dep-partial.mir
  LLVM :: CodeGen/Hexagon/branchfolder-keep-impdef.ll
  LLVM :: CodeGen/Hexagon/regalloc-bad-undef.mir
  LLVM :: CodeGen/MIR/X86/callee-saved-info.mir
  LLVM :: CodeGen/MIR/X86/cfi-offset.mir
  LLVM :: CodeGen/MIR/X86/diexpr-win32.mir
  LLVM :: CodeGen/MIR/X86/early-clobber-register-flag.mir
  LLVM :: CodeGen/MIR/X86/expected-different-implicit-operand.mir
  LLVM :: CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
  LLVM :: CodeGen/MIR/X86/external-symbol-operands.mir
  LLVM :: CodeGen/MIR/X86/frame-info-stack-references.mir
  LLVM :: CodeGen/MIR/X86/frame-setup-instruction-flag.mir
  LLVM :: CodeGen/MIR/X86/memory-operands.mir
  LLVM :: CodeGen/MIR/X86/missing-implicit-operand.mir
  LLVM :: CodeGen/MIR/X86/register-mask-operands.mir
  LLVM :: CodeGen/MIR/X86/undef-register-flag.mir
  LLVM :: CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
  LLVM :: CodeGen/PowerPC/aantidep-inline-asm-use.ll
  LLVM :: CodeGen/PowerPC/aix-vsx-splatimm.ll
  LLVM :: CodeGen/PowerPC/atomic-minmax.ll
  LLVM :: CodeGen/PowerPC/bdzlr.ll
  LLVM :: CodeGen/PowerPC/branch-hint.ll
  LLVM :: CodeGen/PowerPC/cmp_elimination.ll
  LLVM :: CodeGen/PowerPC/cr-spills.ll
  LLVM :: CodeGen/PowerPC/crash.ll
  LLVM :: CodeGen/PowerPC/crbit-asm.ll
  LLVM :: CodeGen/PowerPC/crbits.ll
  LLVM :: CodeGen/PowerPC/ctr-cleanup.ll
  LLVM :: CodeGen/PowerPC/ctrloop-le.ll
  LLVM :: CodeGen/PowerPC/ctrloop-lt.ll
  LLVM :: CodeGen/PowerPC/ctrloop-ne.ll
  LLVM :: CodeGen/PowerPC/ctrloop-sums.ll
  LLVM :: CodeGen/PowerPC/ctrloop-udivti3.ll
  LLVM :: CodeGen/PowerPC/ctrloops.ll
  LLVM :: CodeGen/PowerPC/ctrloops32.mir
  LLVM :: CodeGen/PowerPC/ctrloops64.mir
  LLVM :: CodeGen/PowerPC/dform-pair-load-store.ll
  LLVM :: CodeGen/PowerPC/early-ret.ll
  LLVM :: CodeGen/PowerPC/early-ret2.ll
  LLVM :: CodeGen/PowerPC/expand-isel.ll
  LLVM :: CodeGen/PowerPC/f128-aggregates.ll
  LLVM :: CodeGen/PowerPC/f128-compare.ll
  LLVM :: CodeGen/PowerPC/fsel.ll
  LLVM :: CodeGen/PowerPC/htm-ttest.ll
  LLVM :: CodeGen/PowerPC/i1-ext-fold.ll
  LLVM :: CodeGen/PowerPC/lbzux.ll
  LLVM :: CodeGen/PowerPC/loop-align.ll
  LLVM :: CodeGen/PowerPC/loop-p10-pair-prepare.ll
  LLVM :: CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
  LLVM :: CodeGen/PowerPC/merge-st-chain-op.ll
  LLVM :: CodeGen/PowerPC/misched-inorder-latency.ll
  LLVM :: CodeGen/PowerPC/mma-intrinsics.ll
  LLVM :: CodeGen/PowerPC/negctr.ll
  LLVM :: CodeGen/PowerPC/noPermuteFormasking.ll
  LLVM :: CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
  LLVM :: CodeGen/PowerPC/optcmp.ll
  LLVM :: CodeGen/PowerPC/optimize-andiso.ll
  LLVM :: CodeGen/PowerPC/ppc-ctr-dead-code.ll
  LLVM :: CodeGen/PowerPC/ppc-shrink-wrapping.ll
  LLVM :: CodeGen/PowerPC/ppc64-P9-mod.ll
  LLVM :: CodeGen/PowerPC/ppc64-gep-opt.ll
  LLVM :: CodeGen/PowerPC/ppc64-stackmap.ll
  LLVM :: CodeGen/PowerPC/ppcf128-freeze.mir
  LLVM :: CodeGen/PowerPC/pr22711.ll
  LLVM :: CodeGen/PowerPC/pr25157-peephole.ll
  LLVM :: CodeGen/PowerPC/pr25157.ll
  LLVM :: CodeGen/PowerPC/pr47707.ll
  LLVM :: CodeGen/PowerPC/pre-inc-disable.ll
  LLVM :: CodeGen/PowerPC/prefer-dqform.ll
  LLVM :: CodeGen/PowerPC/preinc-ld-sel-crash.ll
  LLVM :: CodeGen/PowerPC/preincprep-nontrans-crash.ll
  LLVM :: CodeGen/PowerPC/rlwimi-and.ll
  LLVM :: CodeGen/PowerPC/scalar-equal.ll
  LLVM :: CodeGen/PowerPC/scalar-min-max.ll
  LLVM :: CodeGen/PowerPC/scalar_cmp.ll
  LLVM :: CodeGen/PowerPC/select-i1-vs-i1.ll
  LLVM :: CodeGen/PowerPC/simplifyConstCmpToISEL.ll
  LLVM :: CodeGen/PowerPC/sj-ctr-loop.ll
  LLVM :: CodeGen/PowerPC/sms-iterator.ll
  LLVM :: CodeGen/PowerPC/sms-phi-5.ll
  LLVM :: CodeGen/PowerPC/store-constant.ll
  LLVM :: CodeGen/PowerPC/stwu-sched.ll
  LLVM :: CodeGen/PowerPC/stwux.ll
  LLVM :: CodeGen/PowerPC/vec-bswap.ll
  LLVM :: CodeGen/PowerPC/vec_select.ll
  LLVM :: CodeGen/PowerPC/vsel-prom.ll
  LLVM :: CodeGen/PowerPC/vsx-fma-mutate-undef.ll
  LLVM :: CodeGen/PowerPC/vsx.ll
  LLVM :: CodeGen/PowerPC/xvcmpeqdp-v2f64.ll
  LLVM :: CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
  LLVM :: CodeGen/SystemZ/clear-liverange-spillreg.mir
  LLVM :: CodeGen/SystemZ/cond-move-04.mir
  LLVM :: CodeGen/SystemZ/cond-move-08.mir
  LLVM :: CodeGen/SystemZ/cond-move-regalloc-hints.mir
  LLVM :: CodeGen/Thumb/constants.ll
  LLVM :: CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
  LLVM :: CodeGen/Thumb2/abs.ll
  LLVM :: CodeGen/Thumb2/mve-abs.ll
  LLVM :: CodeGen/Thumb2/mve-blockplacement.ll
  LLVM :: CodeGen/Thumb2/mve-complex-deinterleaving-i64-add.ll
  LLVM :: CodeGen/Thumb2/mve-laneinterleaving-cost.ll
  LLVM :: CodeGen/Thumb2/mve-laneinterleaving.ll
  LLVM :: CodeGen/Thumb2/mve-masked-ldst.ll
  LLVM :: CodeGen/Thumb2/mve-masked-load.ll
  LLVM :: CodeGen/Thumb2/mve-masked-store.ll
  LLVM :: CodeGen/Thumb2/mve-minmax.ll
  LLVM :: CodeGen/Thumb2/mve-minmaxi.ll
  LLVM :: CodeGen/Thumb2/mve-neg.ll
  LLVM :: CodeGen/Thumb2/mve-pred-ext.ll
  LLVM :: CodeGen/Thumb2/mve-satmul-loops.ll
  LLVM :: CodeGen/Thumb2/mve-saturating-arith.ll
  LLVM :: CodeGen/Thumb2/mve-simple-arith.ll
  LLVM :: CodeGen/Thumb2/mve-vcmp.ll
  LLVM :: CodeGen/Thumb2/mve-vcmpr.ll
  LLVM :: CodeGen/Thumb2/mve-vecreduce-add.ll
  LLVM :: CodeGen/Thumb2/mve-vecreduce-addpred.ll
  LLVM :: CodeGen/Thumb2/mve-vecreduce-mla.ll
  LLVM :: CodeGen/Thumb2/mve-vecreduce-mlapred.ll
  LLVM :: CodeGen/Thumb2/mve-vld2-post.ll
  LLVM :: CodeGen/Thumb2/mve-vld2.ll
  LLVM :: CodeGen/Thumb2/mve-vld3.ll
  LLVM :: CodeGen/Thumb2/mve-vld4-post.ll
  LLVM :: CodeGen/Thumb2/mve-vld4.ll
  LLVM :: CodeGen/Thumb2/mve-vqdmulh.ll
  LLVM :: CodeGen/Thumb2/mve-vqmovn.ll
  LLVM :: CodeGen/Thumb2/mve-vqshrn.ll
  LLVM :: CodeGen/WebAssembly/atomic-fence.mir
  LLVM :: CodeGen/X86/block-placement.mir
  LLVM :: CodeGen/X86/conditional-tailcall-samedest.mir
  LLVM :: CodeGen/X86/crash.ll
  LLVM :: CodeGen/X86/implicit-null-checks.mir
  LLVM :: CodeGen/X86/machine-copy-prop.mir
  LLVM :: CodeGen/X86/non-value-mem-operand.mir
  LLVM :: CodeGen/X86/post-ra-sched-with-debug.mir
  LLVM :: CodeGen/X86/retpoline-external.ll
  LLVM :: CodeGen/X86/retpoline-regparm.ll
  LLVM :: CodeGen/X86/retpoline.ll
  LLVM :: CodeGen/X86/swifterror.ll
  LLVM :: CodeGen/X86/tail-call-conditional.mir
  LLVM :: CodeGen/X86/update-terminator.mir
  LLVM :: DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
  LLVM :: DebugInfo/MIR/X86/live-debug-values-spill.mir
  LLVM :: DebugInfo/MIR/X86/live-debug-values.mir
  LLVM :: DebugInfo/MIR/X86/livedebugvalues-limit.mir
  LLVM :: DebugInfo/MIR/X86/no-cfi-loc.mir
  LLVM-Unit :: Target/AArch64/./AArch64Tests/2/17
  LLVM-Unit :: Target/AArch64/./AArch64Tests/7/17

llvm/lib/CodeGen/MIRParser/MIParser.cpp

private:
   /// Otherwise return false.
   bool consumeIfPresent(MIToken::TokenKind TokenKind);
 
   bool parseInstruction(unsigned &OpCode, unsigned &Flags);
 
   bool assignRegisterTies(MachineInstr &MI,
                           ArrayRef<ParsedMachineOperand> Operands);
 
-  bool verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
-                              const MCInstrDesc &MCID);
-
   const BasicBlock *getIRBlock(unsigned Slot);
   const BasicBlock *getIRBlock(unsigned Slot, const Function &F);
 
   /// Get or create an MCSymbol for a given name.
   MCSymbol *getOrCreateMCSymbol(StringRef Name);
 
   /// parseStringConstant
   ///   ::= StringConstant
while (!Token.isNewlineOrEOF()) {
         break;
       if (Token.isNot(MIToken::comma))
         return error("expected ',' before the next machine memory operand");
       lex();
     }
   }
 
   const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
-  if (!MCID.isVariadic()) {
-    // FIXME: Move the implicit operand verification to the machine verifier.
-    if (verifyImplicitOperands(Operands, MCID))
-      return true;
-  }
-
   MI = MF.CreateMachineInstr(MCID, DebugLocation, /*NoImplicit=*/true);
   MI->setFlags(Flags);
 
   unsigned NumExplicitOps = 0;
   for (const auto &Operand : Operands) {
     bool IsImplicitOp = Operand.Operand.isReg() && Operand.Operand.isImplicit();
     if (!IsImplicitOp) {
       if (!MCID.isVariadic() && NumExplicitOps >= MCID.getNumOperands() &&
bool MIParser::parseMetadata(Metadata *&MD) {
   FwdRef = std::make_pair(
       MDTuple::getTemporary(MF.getFunction().getContext(), std::nullopt), Loc);
   PFS.MachineMetadataNodes[ID].reset(FwdRef.first.get());
   MD = FwdRef.first.get();
 
   return false;
 }
 
-static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
-  assert(MO.isImplicit());
-  return MO.isDef() ? "implicit-def" : "implicit";
-}
-
-static std::string getRegisterName(const TargetRegisterInfo *TRI,
-                                   Register Reg) {
-  assert(Register::isPhysicalRegister(Reg) && "expected phys reg");
-  return StringRef(TRI->getName(Reg)).lower();
-}
-
-/// Return true if the parsed machine operands contain a given machine operand.
-static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand,
-                                ArrayRef<ParsedMachineOperand> Operands) {
-  for (const auto &I : Operands) {
-    if (ImplicitOperand.isIdenticalTo(I.Operand))
-      return true;
-  }
-  return false;
-}
-
-bool MIParser::verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
-                                      const MCInstrDesc &MCID) {
-  if (MCID.isCall())
-    // We can't verify call instructions as they can contain arbitrary implicit
-    // register and register mask operands.
-    return false;
-
-  // Gather all the expected implicit operands.
-  SmallVector<MachineOperand, 4> ImplicitOperands;
-  if (MCID.getImplicitDefs())
-    for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
-      ImplicitOperands.push_back(
-          MachineOperand::CreateReg(*ImpDefs, true, true));
-  if (MCID.getImplicitUses())
-    for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
-      ImplicitOperands.push_back(
-          MachineOperand::CreateReg(*ImpUses, false, true));
-
-  const auto *TRI = MF.getSubtarget().getRegisterInfo();
-  assert(TRI && "Expected target register info");
-  for (const auto &I : ImplicitOperands) {
-    if (isImplicitOperandIn(I, Operands))
-      continue;
-    return error(Operands.empty() ? Token.location() : Operands.back().End,
-                 Twine("missing implicit register operand '") +
-                     printImplicitRegisterFlag(I) + " $" +
-                     getRegisterName(TRI, I.getReg()) + "'");
-  }
-  return false;
-}
-
 bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
   // Allow frame and fast math flags for OPCODE
   while (Token.is(MIToken::kw_frame_setup) ||
          Token.is(MIToken::kw_frame_destroy) ||
          Token.is(MIToken::kw_nnan) ||
          Token.is(MIToken::kw_ninf) ||
          Token.is(MIToken::kw_nsz) ||
          Token.is(MIToken::kw_arcp) ||

llvm/lib/CodeGen/MachineVerifier.cpp

 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   const MCInstrDesc &MCID = MI->getDesc();
   if (MI->getNumOperands() < MCID.getNumOperands()) {
     report("Too few operands", MI);
     errs() << MCID.getNumOperands() << " operands expected, but "
            << MI->getNumOperands() << " given.\n";
   }
 
+  if (MCID.getImplicitDefs()) {
+    for (const MCPhysReg *I = MCID.getImplicitDefs(); *I; ++I) {
+      if (none_of(MI->implicit_operands(), [I](const MachineOperand &Op) {
+            return Op.isReg() && Op.isDef() && Op.getReg() == *I;
+          })) {
+        report("Missing implicit def", MI);
+        report_context(MCPhysReg(*I));
+      }
+    }
+  }
+
+  if (MCID.getImplicitUses()) {
+    for (const MCPhysReg *I = MCID.getImplicitUses(); *I; ++I) {
+      if (none_of(MI->implicit_operands(), [I](const MachineOperand &Op) {
+            return Op.isReg() && Op.isUse() && Op.getReg() == *I;
+          })) {
+        report("Missing implicit use", MI);
+        report_context(MCPhysReg(*I));
+      }
+    }
+  }
+
   if (MI->isPHI()) {
     if (MF->getProperties().hasProperty(
             MachineFunctionProperties::Property::NoPHIs))
       report("Found PHI instruction with NoPHIs property set", MI);
 
     if (FirstNonPHI)
       report("Found PHI instruction after non-PHI", MI);
   } else if (FirstNonPHI == nullptr)