[EarlyIfConversion] Add target hook to allow for multiple ifcvt iterations.

[hgreving]

Summary

Adds a target hook canPredicatePredicatedInstr(const MachineInstr&) that
assumes an instruction is already predicated and returns true if it can
be predicated again, used by the early if-conversion pass in order to
iterate multiple times on architectures supporting predicate logic.

No test added since there is no upstream target that can take advantage.

[hgreving]

Hi I've added reviewers from the git log. I wonder if this change is acceptable which would help us avoiding to downstream the entire pass. Thanks in advance

[arsenm]

llvm/lib/CodeGen/EarlyIfConversion.cpp

57

A command line flag isn’t the way to expose this. I would move this into a partner bit with isPredicable, maybe combining into a predicable kind field

[hgreving]

llvm/lib/CodeGen/EarlyIfConversion.cpp

57

Thanks for the comment. The reason (I agree) I just added this switch is that it is a property / tweak of the pass, and only applies to archs where a predicable instruction "is predicated". On Hexagon, a predicted instruction (AFAICS, had to dig in more) is _not_ predicable. On x86, an instruction never returns isPredicated (I guess this makes sense). ARM/AArch64 not 100% sure.

WDYT about a TII->canPredicatePredicatedIntrs() hook? Reason being this is more a property of the arch being able to support predicate logic rather than a property of each intruction.

Also problem is which architecture could I test this with :(?

[jroelofs]

llvm/lib/CodeGen/EarlyIfConversion.cpp

57

A TII hook seems appropriate. How about TII->canPredicatePredicatedInstr(*I), so the interface doesn't need to change again when a target comes along that needs to decide per-instruction.

[hgreving]

llvm/lib/CodeGen/EarlyIfConversion.cpp

57

PTAL

57

PTAL

[jroelofs]

LGTM

[hgreving]

Thanks for review.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   virtual MCInst getNop() const;
 
   /// Return true for post-incremented instructions.
   virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
 
   /// Returns true if the instruction is already predicated.
   virtual bool isPredicated(const MachineInstr &MI) const { return false; }
 
+  /// Assumes the instruction is already predicated and returns true if the
+  /// instruction can be predicated again.
+  virtual bool canPredicatePredicatedInstr(const MachineInstr &MI) const {
+    assert(isPredicated(MI) && "Instruction is not predicated");
+    return false;
+  }
+
   // Returns a MIRPrinter comment for this machine operand.
   virtual std::string
   createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
                           unsigned OpIdx, const TargetRegisterInfo *TRI) const;
 
   /// Returns true if the instruction is a
   /// terminator instruction that has not been predicated.
   bool isUnpredicatedTerminator(const MachineInstr &MI) const;

llvm/lib/CodeGen/EarlyIfConversion.cpp

BlockInstrLimit("early-ifcvt-limit", cl::init(30), cl::Hidden,
   cl::desc("Maximum number of instructions per speculated block."));
 
 // Stress testing mode - disable heuristics.
 static cl::opt<bool> Stress("stress-early-ifcvt", cl::Hidden,
   cl::desc("Turn all knobs to 11"));
 
 STATISTIC(NumDiamondsSeen,  "Number of diamonds");
 STATISTIC(NumDiamondsConv,  "Number of diamonds converted");
 STATISTIC(NumTrianglesSeen, "Number of triangles");
 STATISTIC(NumTrianglesConv, "Number of triangles converted");
 
 //===----------------------------------------------------------------------===//
 //                                 SSAIfConv
 //===----------------------------------------------------------------------===//
 //
 // The SSAIfConv class performs if-conversion on SSA form machine code after
 // determining if it is possible. The class contains no heuristics; external
for (MachineBasicBlock::iterator I = MBB->begin(),
     }
 
     // There shouldn't normally be any phis in a single-predecessor block.
     if (I->isPHI()) {
       LLVM_DEBUG(dbgs() << "Can't predicate: " << *I);
       return false;
     }
 
-    // Check that instruction is predicable and that it is not already
-    // predicated.
-    if (!TII->isPredicable(*I) || TII->isPredicated(*I)) {
+    // Check that instruction is predicable
+    if (!TII->isPredicable(*I)) {
+      LLVM_DEBUG(dbgs() << "Isn't predicable: " << *I);
+      return false;
+    }
+
+    // Check that instruction is not already predicated.
+    if (TII->isPredicated(*I) && !TII->canPredicatePredicatedInstr(*I)) {
+      LLVM_DEBUG(dbgs() << "Is already predicated: " << *I);
       return false;
     }
 
     // Check for any dependencies on Head instructions.
     if (!InstrDependenciesAllowIfConv(&(*I)))
       return false;
   }
   return true;