[AVR] Support 16-bit LDS/STS on AVRTiny.

[benshi001]

Summary

LDS/STS are 32-bit instructions on AVR, which can access 64KB data
space. While they are 16-bit instructions on AVRTiny, which can
only access 128B data space.

[benshi001]

fixes https://github.com/llvm/llvm-project/issues/58876

[aykevl]

Looks good to me!

llvm/lib/Target/AVR/AVRInstrFormats.td

class F32DM<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
 
   let Inst{23 - 20} = rd{3 - 0};
 
   let Inst{19 - 16} = 0b0000;
 
   let Inst{15 - 0} = k;
 }
 
+//===---------------------------------------------------------------------===//
+// Special format for the LDS/STS instructions on AVRTiny.
+// <|1010|ikkk|dddd|kkkk>
+// d = R16 ~ R31
+// i = 0 - lds, 1 - sts
+// k = 7-bit data space address
+//===---------------------------------------------------------------------===//
+class FLDSSTSTINY<bit i, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : AVRInst16<outs, ins, asmstr, pattern> {
+  bits<5> rd;
+  bits<7> k;
+
+  let Inst{15 - 12} = 0b1010;
+
+  let Inst{11} = i;
+
+  let Inst{10 - 8} = k{6 - 4};
+  let Inst{7 - 4} = rd{3 - 0};
+  let Inst{3 - 0} = k{3 - 0};
+
+  let DecoderNamespace = "AVRTiny";
+}
+
 // <|1001|0100|bfff|1000>
 class FS<bit b, dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
   bits<3> s;
 
   let Inst{15 - 12} = 0b1001;
 
   let Inst{11 - 8} = 0b0100;

llvm/lib/Target/AVR/AVRInstrInfo.td

 def call_target : Operand<iPTR> {
   let EncoderMethod = "encodeCallTarget";
   let DecoderMethod = "decodeCallTarget";
 }
 
 // A 16-bit address (which can lead to an R_AVR_16 relocation).
 def imm16 : Operand<i16> { let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; }
 
+// A 7-bit address (which can lead to an R_AVR_LDS_STS_16 relocation).
+def imm7tiny : Operand<i8> {
+  let EncoderMethod = "encodeImm<AVR::fixup_lds_sts_16, 0>";
+}
+
 /// A 6-bit immediate used in the ADIW/SBIW instructions.
 def imm_arith6 : Operand<i16> {
   let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";
 }
 
 /// An 8-bit immediate inside an instruction with the same format
 /// as the `LDI` instruction (the `FRdK` format).
 def imm_ldi8 : Operand<i8> {
def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,
                              AssemblerPredicate<(all_of FeatureMultiplication)>;
 
 def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
                AssemblerPredicate<(all_of FeatureBREAK)>;
 
 def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,
                       AssemblerPredicate<(all_of FeatureTinyEncoding)>;
 
+def HasNonTinyEncoding : Predicate<"!Subtarget->hasTinyEncoding()">,
+                         AssemblerPredicate<(any_of (not FeatureTinyEncoding))>;
+
 // AVR specific condition code. These correspond to AVR_*_COND in
 // AVRInstrInfo.td. They must be kept in synch.
 def AVR_COND_EQ : PatLeaf<(i8 0)>;
 def AVR_COND_NE : PatLeaf<(i8 1)>;
 def AVR_COND_GE : PatLeaf<(i8 2)>;
 def AVR_COND_LT : PatLeaf<(i8 3)>;
 def AVR_COND_SH : PatLeaf<(i8 4)>;
 def AVR_COND_LO : PatLeaf<(i8 5)>;
let canFoldAsLoad = 1, isReMaterializable = 1 in {
   def LDSRdK : F32DM<0b0,
                      (outs GPR8
                       : $rd),
                      (ins imm16
                       : $k),
                      "lds\t$rd, $k", [(set i8
                                        : $rd, (load imm
                                                : $k))]>,
-               Requires<[HasSRAM]>;
+               Requires<[HasSRAM, HasNonTinyEncoding]>;
+
+  // Load from data space into register, which is only available on AVRTiny.
+  def LDSRdKTiny : FLDSSTSTINY<0b0, (outs LD8:$rd), (ins imm7tiny:$k),
+                               "lds\t$rd, $k", []>,
+                   Requires<[HasSRAM, HasTinyEncoding]>;
 
   // LDSW Rd+1:Rd, K+1:K
   //
   // Expands to:
   // lds Rd,  (K+1:K)
   // lds Rd+1 (K+1:K) + 1
   def LDSWRdK : Pseudo<(outs DREGS
                         : $dst),

 // Indirect store from register to data space.
 def STSKRr : F32DM<0b1, (outs),
                    (ins imm16
                     : $k, GPR8
                     : $rd),
                    "sts\t$k, $rd", [(store i8
                                      : $rd, imm
                                      : $k)]>,
-             Requires<[HasSRAM]>;
+             Requires<[HasSRAM, HasNonTinyEncoding]>;
+
+// Store from register to data space, which is only available on AVRTiny.
+def STSKRrTiny : FLDSSTSTINY<0b1, (outs), (ins imm7tiny:$k, LD8:$rd),
+                             "sts\t$k, $rd", []>,
+                 Requires<[HasSRAM, HasTinyEncoding]>;
 
 // STSW K+1:K, Rr+1:Rr
 //
 // Expands to:
 // sts Rr+1, (K+1:K) + 1
 // sts Rr,   (K+1:K)
 def STSWKRr : Pseudo<(outs),
                      (ins i16imm

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 
   // Try decode a 16-bit instruction.
   {
     Result = readInstruction16(Bytes, Address, Size, Insn);
 
     if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
 
+    // Try to decode AVRTiny instructions.
+    if (STI.getFeatureBits()[AVR::FeatureTinyEncoding]) {
+      Result = decodeInstruction(DecoderTableAVRTiny16, Instr, Insn, Address,
+                                 this, STI);
+      if (Result != MCDisassembler::Fail)
+        return Result;
+    }
+
     // Try to auto-decode a 16-bit instruction.
     Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address,
                                this, STI);
     if (Result != MCDisassembler::Fail)
       return Result;
 
     // Try to decode to a load/store instruction. ST/LD need a specified
     // DecoderMethod, as they already have a specified PostEncoderMethod.

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

 /// 1011 0AAd dddd AAAA
 static void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
                         MCContext *Ctx = nullptr) {
   unsigned_width(6, Value, std::string("port number"), Fixup, Ctx);
 
   Value = ((Value & 0x30) << 5) | (Value & 0x0f);
 }
 
+/// 7-bit data space address fixup for the LDS/STS instructions on AVRTiny.
+///
+/// Resolves to:
+/// 1010 ikkk dddd kkkk
+static void fixup_lds_sts_16(const MCFixup &Fixup, uint64_t &Value,
+                             MCContext *Ctx = nullptr) {
+  unsigned_width(7, Value, std::string("immediate"), Fixup, Ctx);
+  Value = ((Value & 0x70) << 8) | (Value & 0x0f);
+}
+
 /// Adjusts a program memory address.
 /// This is a simple right-shift.
 static void pm(uint64_t &Value) { Value >>= 1; }
 
 /// Fixups relating to the LDI instruction.
 namespace ldi {
 
 /// Adjusts a value to fix up the immediate of an `LDI Rd, K` instruction.
void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup,
   case AVR::fixup_port5:
     adjust::fixup_port5(Fixup, Value, Ctx);
     break;
 
   case AVR::fixup_port6:
     adjust::fixup_port6(Fixup, Value, Ctx);
     break;
 
+  case AVR::fixup_lds_sts_16:
+    adjust::fixup_lds_sts_16(Fixup, Value, Ctx);
+    break;
+
   // Fixups which do not require adjustments.
   case FK_Data_1:
   case FK_Data_2:
   case FK_Data_4:
   case FK_Data_8:
     break;
 
   case FK_GPRel_4:

llvm/test/MC/AVR/inst-lds-tiny.s

+; RUN: llvm-mc -triple avr -mattr=sram,tinyencoding -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram,tinyencoding < %s | llvm-objdump --no-print-imm-hex -dr --mattr=sram,tinyencoding - | FileCheck -check-prefix=CHECK-INST %s
+
+foo:
+  lds r16, 113
+  lds r29, 62
+  lds r22, 44
+  lds r27, 92
+  lds r20, SYMBOL+12
+
+; CHECK:  lds r16, 113                 ; encoding: [0x01,0xa7]
+; CHECK:  lds r29, 62                  ; encoding: [0xde,0xa3]
+; CHECK:  lds r22, 44                  ; encoding: [0x6c,0xa2]
+; CHECK:  lds r27, 92                  ; encoding: [0xbc,0xa5]
+; CHECK:  lds r20, SYMBOL+12           ; encoding: [0x40'A',0xa0'A']
+; CHECK:                               ; fixup A - offset: 0, value: SYMBOL+12, kind: fixup_lds_sts_16
+
+; CHECK-INST: lds r16, 113
+; CHECK-INST: lds r29, 62
+; CHECK-INST: lds r22, 44
+; CHECK-INST: lds r27, 92
+; CHECK-INST: lds r20,  0
+; CHECK-INST: R_AVR_LDS_STS_16 SYMBOL+0xc

llvm/test/MC/AVR/inst-sts-tiny.s

+; RUN: llvm-mc -triple avr -mattr=sram,tinyencoding -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram,tinyencoding < %s | llvm-objdump --no-print-imm-hex -dr --mattr=sram,tinyencoding - | FileCheck -check-prefix=CHECK-INST %s
+
+foo:
+  sts 3,        r16
+  sts 127,      r17
+  sts SYMBOL+1, r25
+
+; CHECK:  sts 3,        r16           ; encoding: [0x03,0xa8]
+; CHECK:  sts 127,      r17           ; encoding: [0x1f,0xaf]
+; CHECK:  sts SYMBOL+1, r25           ; encoding: [0x90'A',0xa8'A']
+; CHECK:                              ; fixup A - offset: 0, value: SYMBOL+1, kind: fixup_lds_sts_16
+
+; CHECK-INST: sts 3,   r16
+; CHECK-INST: sts 127, r17
+; CHECK-INST: sts 0,   r25
+; CHECK-INST: R_AVR_LDS_STS_16 SYMBOL+0x1