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Differential D13885

[mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt
ClosedPublic

Authored by hvarga on Oct 20 2015, 3:50 AM.

Details

Reviewers
dsanders
zbuljan
zoran.jovanovic
Commits
rL254405: [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt…
Summary

The patch implements microMIPS32r6 and microMIPS64r6 RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt FPU instructions.

Diff Detail

Event Timeline

hvarga updated this revision to Diff 37847.Oct 20 2015, 3:50 AM
hvarga retitled this revision from to [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt.
hvarga updated this object.
hvarga added reviewers: zoran.jovanovic, zbuljan, dsanders.
hvarga added subscribers: petarj, llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptOct 20 2015, 3:50 AM
dsanders requested changes to this revision.Oct 22 2015, 7:33 AM
dsanders edited edge metadata.

If you're using the web interface to create the review, please remember to include the full context as described at http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

My main concern is the removal of several FPU instructions from 32R6 and 64R6.

lib/Target/Mips/MicroMips32r6InstrInfo.td
115

RECIP -> RECIP_D

117

RINT -> RINT_D

120

ROUND_L -> ROUND_L_D

124

ROUND_W -> ROUND_W_D

127

SEL -> SEL_D

714–725

I should have mentioned this sooner but ABSS_FT_MMR6_DESC_BASE seems to have become a generic 2-operand description. This being the case, could you rename it (in a follow-up patch)? It seems strange to see RECIP.S (etc.) described as being an absolute operation.

716

RECIP -> RECIP_D

720

ROUND_L -> ROUND_L_D

724

ROUND_W -> ROUND_W_D

728

SEL -> SEL_D

738

RINT -> RINT_D

1053

RECIP -> RECIP_D

1056

RINT -> RINT_D

1059

ROUND_L -> ROUND_L_D

1063

ROUND_W -> ROUND_W_D

1066

SEL -> SEL_D

lib/Target/Mips/Mips32r6InstrInfo.td
716–725

Please move these back to where they were and use a separate 'let AdditionalPredicates ...'. They were in documentation order.

lib/Target/Mips/MipsInstrFPU.td
270–279

Why have you removed these from 32R6/64R6? 32R6/64R6 didn't change these instructions

Also, multiple ISA_*'s on the same instruction doesn't work since it overrides the same sub-list from PredicateControl.

This revision now requires changes to proceed.Oct 22 2015, 7:33 AM
hvarga updated this revision to Diff 40277.Nov 16 2015, 5:13 AM
hvarga edited edge metadata.

Fix comments recieved from dsanders.

dsanders accepted this revision.Nov 27 2015, 1:54 AM
dsanders edited edge metadata.

LGTM with a possible nit

lib/Target/Mips/MicroMips32r6InstrInfo.td
1166

80 cols? It looks long but I haven't counted.

This revision is now accepted and ready to land.Nov 27 2015, 1:54 AM
Closed by commit rL254405: [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt… (authored by hvarga). · Explain WhyDec 1 2015, 4:02 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
62 lines
75 lines
36 lines
15 lines
test/
MC/
Disassembler/
Mips/
micromips32r6/
16 lines
micromips64r6/
16 lines
Mips/
micromips32r6/
16 lines
micromips64r6/
16 lines

Diff 37847

lib/Target/Mips/MicroMips32r6InstrFormats.td

Context not available.
let Inst{15-6} = funct; let Inst{15-6} = funct;
let Inst{5-0} = 0x3c; let Inst{5-0} = 0x3c;
} }
class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> ft;
bits<5> fs;
bits<32> Inst;
let Inst{31-26} = 0b010101;
let Inst{25-21} = ft;
let Inst{20-16} = fs;
let Inst{15} = 0;
let Inst{14} = fmt;
let Inst{13-6} = funct;
let Inst{5-0} = 0b111011;
}
class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> fs;
bits<5> fd;
bits<32> Inst;
let Inst{31-26} = 0b010101;
let Inst{25-21} = fs;
let Inst{20-16} = fd;
let Inst{15-11} = 0;
let Inst{10-9} = fmt;
let Inst{8-0} = 0b000100000;
}
class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> ft;
bits<5> fs;
bits<5> fd;
bits<32> Inst;
let Inst{31-26} = 0b010101;
let Inst{25-21} = ft;
let Inst{20-16} = fs;
let Inst{15-11} = fd;
let Inst{10-9} = fmt;
let Inst{8-0} = funct;
}
class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> fs;
bits<5> fd;
bits<32> Inst;
let Inst{31-26} = 0b010101;
let Inst{25-21} = fs;
let Inst{20-16} = fd;
let Inst{15-11} = 0b00000;
let Inst{10-9} = fmt;
let Inst{8-0} = funct;
}
Context not available.

lib/Target/Mips/MicroMips32r6InstrInfo.td

Context not available.
class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
class RECIP_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
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RECIP -> RECIP_D

dsanders: RECIP -> RECIP_D
class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
class RINT_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
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RINT -> RINT_D

dsanders: RINT -> RINT_D
class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
0b11001100>;
class ROUND_L_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
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ROUND_L -> ROUND_L_D

dsanders: ROUND_L -> ROUND_L_D
0b11001100>;
class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
0b11101100>;
class ROUND_W_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
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ROUND_W -> ROUND_W_D

dsanders: ROUND_W -> ROUND_W_D
0b11101100>;
class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
class SEL_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
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SEL -> SEL_D

dsanders: SEL -> SEL_D
class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
class SELENZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.s", 0, 0b001111000>;
class SELENZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.d", 1, 0b001111000>;
class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6; class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6; class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
Context not available.
FGR32Opnd, II_TRUNC>; FGR32Opnd, II_TRUNC>;
class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd, class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
AFGR64Opnd, II_TRUNC>; AFGR64Opnd, II_TRUNC>;
class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
FGR32Opnd, II_ROUND>;
class RECIP_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
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RECIP -> RECIP_D

dsanders: RECIP -> RECIP_D
II_ROUND>;
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
FGR32Opnd, II_ROUND>;
class ROUND_L_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
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ROUND_L -> ROUND_L_D

dsanders: ROUND_L -> ROUND_L_D
FGR64Opnd, II_ROUND>;
class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
FGR32Opnd, II_ROUND>;
class ROUND_W_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
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ROUND_W -> ROUND_W_D

dsanders: ROUND_W -> ROUND_W_D
FGR64Opnd, II_ROUND>;
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I should have mentioned this sooner but ABSS_FT_MMR6_DESC_BASE seems to have become a generic 2-operand description. This being the case, could you rename it (in a follow-up patch)? It seems strange to see RECIP.S (etc.) described as being an absolute operation.

dsanders: I should have mentioned this sooner but ABSS_FT_MMR6_DESC_BASE seems to have become a generic 2…
class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
class SEL_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
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SEL -> SEL_D

dsanders: SEL -> SEL_D
// We must insert a SUBREG_TO_REG around $fd_in
bit usesCustomInserter = 1;
}
class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
class SELENZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
class SELENZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
class RINT_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
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RINT -> RINT_D

dsanders: RINT -> RINT_D
class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO> class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
: Store<opstr, RO>, MMR6Arch<opstr> { : Store<opstr, RO>, MMR6Arch<opstr> {
Context not available.
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC, def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def RECIP_MMR6 : StdMMR6Rel, RECIP_MMR6_ENC, RECIP_MMR6_DESC, ISA_MICROMIPS32R6;
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RECIP -> RECIP_D

dsanders: RECIP -> RECIP_D
def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def RINT_MMR6 : StdMMR6Rel, RINT_MMR6_ENC, RINT_MMR6_DESC, ISA_MICROMIPS32R6;
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RINT -> RINT_D

dsanders: RINT -> RINT_D
def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def ROUND_L_MMR6 : StdMMR6Rel, ROUND_L_MMR6_ENC, ROUND_L_MMR6_DESC,
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ROUND_L -> ROUND_L_D

dsanders: ROUND_L -> ROUND_L_D
ISA_MICROMIPS32R6;
def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def ROUND_W_MMR6 : StdMMR6Rel, ROUND_W_MMR6_ENC, ROUND_W_MMR6_DESC,
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ROUND_W -> ROUND_W_D

dsanders: ROUND_W -> ROUND_W_D
ISA_MICROMIPS32R6;
def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
def SEL_MMR6 : StdMMR6Rel, SEL_MMR6_ENC, SEL_MMR6_DESC, ISA_MICROMIPS32R6;
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SEL -> SEL_D

dsanders: SEL -> SEL_D
def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
ISA_MICROMIPS32R6;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.
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80 cols? It looks long but I haven't counted.

dsanders: 80 cols? It looks long but I haven't counted.

lib/Target/Mips/Mips32r6InstrInfo.td

Context not available.
def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
Context not available.
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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Please move these back to where they were and use a separate 'let AdditionalPredicates ...'. They were in documentation order.

dsanders: Please move these back to where they were and use a separate 'let AdditionalPredicates ...'.
} }
def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6; def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6; def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
Context not available.
def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
def NAL; // BAL with rd=0 def NAL; // BAL with rd=0
def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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lib/Target/Mips/MipsInstrFPU.td

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// Floating Point Instructions // Floating Point Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0xc, 16>, ISA_MIPS2; ABSS_FM<0xc, 16>, ISA_MIPS2, ISA_MIPS2_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in { defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2,
ISA_MIPS2_NOT_32R6_64R6;
def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
ABSS_FM<0xd, 16>, ISA_MIPS2; ABSS_FM<0xd, 16>, ISA_MIPS2, ISA_MIPS2_NOT_32R6_64R6;
def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
ABSS_FM<0xe, 16>, ISA_MIPS2; ABSS_FM<0xe, 16>, ISA_MIPS2, ISA_MIPS2_NOT_32R6_64R6;
def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
ABSS_FM<0xf, 16>, ISA_MIPS2; ABSS_FM<0xf, 16>, ISA_MIPS2, ISA_MIPS2_NOT_32R6_64R6;
dsandersUnsubmitted
Not Done
ReplyInline Actions

Why have you removed these from 32R6/64R6? 32R6/64R6 didn't change these instructions

Also, multiple ISA_*'s on the same instruction doesn't work since it overrides the same sub-list from PredicateControl.

dsanders: Why have you removed these from 32R6/64R6? 32R6/64R6 didn't change these instructions Also…
}
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x24, 16>; ABSS_FM<0x24, 16>;
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
let DecoderNamespace = "Mips64" in { let DecoderNamespace = "Mips64" in {
let AdditionalPredicates = [NotInMicroMips] in {
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0x8, 16>, FGR_64; ABSS_FM<0x8, 16>, FGR_64;
def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
ABSS_FM<0x8, 17>, FGR_64; ABSS_FM<0x8, 17>, FGR_64;
let AdditionalPredicates = [NotInMicroMips] in {
def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
ABSS_FM<0x9, 16>, FGR_64; ABSS_FM<0x9, 16>, FGR_64;
def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
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test/MC/Disassembler/Mips/micromips32r6/valid.txt

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0x14 0x85 0x00 0x08 # CHECK: lbu $4, 8($5) 0x14 0x85 0x00 0x08 # CHECK: lbu $4, 8($5)
0x60 0x85 0x68 0x08 # CHECK: lbe $4, 8($5) 0x60 0x85 0x68 0x08 # CHECK: lbe $4, 8($5)
0x60 0x85 0x60 0x08 # CHECK: lbue $4, 8($5) 0x60 0x85 0x60 0x08 # CHECK: lbue $4, 8($5)
0x54 0x44 0x12 0x3b # CHECK: recip.s $f2, $f4
0x54 0x44 0x52 0x3b # CHECK: recip.d $f2, $f4
0x54 0x82 0x00 0x20 # CHECK: rint.s $f2, $f4
0x54 0x82 0x02 0x20 # CHECK: rint.d $f2, $f4
0x54 0x44 0x33 0x3b # CHECK: round.l.s $f2, $f4
0x54 0x44 0x73 0x3b # CHECK: round.l.d $f2, $f4
0x54 0x44 0x3b 0x3b # CHECK: round.w.s $f2, $f4
0x54 0x44 0x7b 0x3b # CHECK: round.w.d $f2, $f4
0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
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test/MC/Disassembler/Mips/micromips64r6/valid.txt

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0x46 0x3b # CHECK: sdbbp16 8 0x46 0x3b # CHECK: sdbbp16 8
0x04 0x3b # CHECK: subu16 $5, $16, $3 0x04 0x3b # CHECK: subu16 $5, $16, $3
0x44 0xd8 # CHECK: xor16 $17, $5 0x44 0xd8 # CHECK: xor16 $17, $5
0x54 0x44 0x12 0x3b # CHECK: recip.s $f2, $f4
0x54 0x44 0x52 0x3b # CHECK: recip.d $f2, $f4
0x54 0x82 0x00 0x20 # CHECK: rint.s $f2, $f4
0x54 0x82 0x02 0x20 # CHECK: rint.d $f2, $f4
0x54 0x44 0x33 0x3b # CHECK: round.l.s $f2, $f4
0x54 0x44 0x73 0x3b # CHECK: round.l.d $f2, $f4
0x54 0x44 0x3b 0x3b # CHECK: round.w.s $f2, $f4
0x54 0x44 0x7b 0x3b # CHECK: round.w.d $f2, $f4
0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
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test/MC/Mips/micromips32r6/valid.s

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lbu $4, 8($5) # CHECK: lbu $4, 8($5) # encoding: [0x14,0x85,0x00,0x08] lbu $4, 8($5) # CHECK: lbu $4, 8($5) # encoding: [0x14,0x85,0x00,0x08]
lbe $4, 8($5) # CHECK: lbe $4, 8($5) # encoding: [0x60,0x85,0x68,0x08] lbe $4, 8($5) # CHECK: lbe $4, 8($5) # encoding: [0x60,0x85,0x68,0x08]
lbue $4, 8($5) # CHECK: lbue $4, 8($5) # encoding: [0x60,0x85,0x60,0x08] lbue $4, 8($5) # CHECK: lbue $4, 8($5) # encoding: [0x60,0x85,0x60,0x08]
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x54,0x82,0x00,0x20]
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x20]
round.l.s $f2, $f4 # CHECK: round.l.s $f2, $f4 # encoding: [0x54,0x44,0x33,0x3b]
round.l.d $f2, $f4 # CHECK: round.l.d $f2, $f4 # encoding: [0x54,0x44,0x73,0x3b]
round.w.s $f2, $f4 # CHECK: round.w.s $f2, $f4 # encoding: [0x54,0x44,0x3b,0x3b]
round.w.d $f2, $f4 # CHECK: round.w.d $f2, $f4 # encoding: [0x54,0x44,0x7b,0x3b]
sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
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test/MC/Mips/micromips64r6/valid.s

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sdbbp16 8 # CHECK: sdbbp16 8 # encoding: [0x46,0x3b] sdbbp16 8 # CHECK: sdbbp16 8 # encoding: [0x46,0x3b]
subu16 $5, $16, $3 # CHECK: subu16 $5, $16, $3 # encoding: [0x04,0x3b] subu16 $5, $16, $3 # CHECK: subu16 $5, $16, $3 # encoding: [0x04,0x3b]
xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0xd8] xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0xd8]
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x54,0x82,0x00,0x20]
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x20]
round.l.s $f2, $f4 # CHECK: round.l.s $f2, $f4 # encoding: [0x54,0x44,0x33,0x3b]
round.l.d $f2, $f4 # CHECK: round.l.d $f2, $f4 # encoding: [0x54,0x44,0x73,0x3b]
round.w.s $f2, $f4 # CHECK: round.w.s $f2, $f4 # encoding: [0x54,0x44,0x3b,0x3b]
round.w.d $f2, $f4 # CHECK: round.w.d $f2, $f4 # encoding: [0x54,0x44,0x7b,0x3b]
sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
1: 1:
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