[NFC][ASAN][AMDGPU] Use CreateNot/CreateIsNotNull instead of more verbose CreateICMP methods

[jmmartinez]

Manual rebase.

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Instruction *AddressSanitizer::instrumentAMDGPUAddress(
   if (PtrTy->getPointerAddressSpace() != 0)
     return InsertBefore;
   // Instrument generic addresses in supported addressspaces.
   IRBuilder<> IRB(InsertBefore);
   Value *AddrLong = IRB.CreatePointerCast(Addr, IRB.getInt8PtrTy());
   Value *IsShared = IRB.CreateCall(AMDGPUAddressShared, {AddrLong});
   Value *IsPrivate = IRB.CreateCall(AMDGPUAddressPrivate, {AddrLong});
   Value *IsSharedOrPrivate = IRB.CreateOr(IsShared, IsPrivate);
-  Value *Cmp = IRB.CreateICmpNE(IRB.getTrue(), IsSharedOrPrivate);
+  Value *Cmp = IRB.CreateNot(IsSharedOrPrivate);
   Value *AddrSpaceZeroLanding =
       SplitBlockAndInsertIfThen(Cmp, InsertBefore, false);
   InsertBefore = cast<Instruction>(AddrSpaceZeroLanding);
   return InsertBefore;
 }
 
 void AddressSanitizer::instrumentAddress(Instruction *OrigIns,
                                          Instruction *InsertBefore, Value *Addr,
else
                      {AddrLong, ConstantInt::get(IRB.getInt32Ty(), Exp)});
     return;
   }
 
   Type *ShadowTy =
       IntegerType::get(*C, std::max(8U, TypeSize >> Mapping.Scale));
   Type *ShadowPtrTy = PointerType::get(ShadowTy, 0);
   Value *ShadowPtr = memToShadow(AddrLong, IRB);
-  Value *CmpVal = Constant::getNullValue(ShadowTy);
   Value *ShadowValue =
       IRB.CreateLoad(ShadowTy, IRB.CreateIntToPtr(ShadowPtr, ShadowPtrTy));
 
-  Value *Cmp = IRB.CreateICmpNE(ShadowValue, CmpVal);
+  Value *Cmp = IRB.CreateIsNotNull(ShadowValue);
   size_t Granularity = 1ULL << Mapping.Scale;
   Instruction *CrashTerm = nullptr;
 
   if (ClAlwaysSlowPath || (TypeSize < 8 * Granularity)) {
     // We use branch weights for the slow path check, to indicate that the slow
     // path is rarely taken. This seems to be the case for SPEC benchmarks.
     Instruction *CheckTerm = SplitBlockAndInsertIfThen(
         Cmp, InsertBefore, false, MDBuilder(*C).createBranchWeights(1, 100000));

llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll

 ; RUN: opt < %s -passes=asan -S | FileCheck %s
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
 target triple = "amdgcn-amd-amdhsa"
 
 define protected amdgpu_kernel void @generic_store(i32 addrspace(1)* %p, i32 %i) sanitize_address {
 entry:
 ; CHECK-LABEL: @generic_store
 ; CHECK-NOT: store
 ; CHECK:   %[[GENERIC_ADDR:[^ ]*]] = bitcast i32* %q to i8*
 ; CHECK:   call i1 @llvm.amdgcn.is.shared(i8* %[[GENERIC_ADDR]])
 ; CHECK:   call i1 @llvm.amdgcn.is.private(i8* %[[GENERIC_ADDR]])
 ; CHECK:   or
-; CHECK:   icmp ne i1 
+; CHECK:   xor i1 %{{.*}}, true
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
 ; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8

 define protected amdgpu_kernel void @generic_load(i32 addrspace(1)* %p, i32 %i) sanitize_address {
 entry:
 ; CHECK-LABEL: @generic_load
 ; CHECK-NOT: load
 ; CHECK:   %[[GENERIC_ADDR:[^ ]*]] = bitcast i32* %q to i8*
 ; CHECK:   call i1 @llvm.amdgcn.is.shared(i8* %[[GENERIC_ADDR]])
 ; CHECK:   call i1 @llvm.amdgcn.is.private(i8* %[[GENERIC_ADDR]])
 ; CHECK:   or
-; CHECK:   icmp ne i1 
+; CHECK:   xor i1 %{{.*}}, true
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
 ; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8