[AVR] Do not use R0/R1 on avrtiny

[aykevl]

Summary

This patch makes sure the compiler uses R16/R17 on avrtiny (attiny10 etc) instead of R0/R1.

Some notes:

• For the NEGW and ROLB instructions, it adds an explicit zero register. This is necessary because the zero register is different on avrtiny (and InstrInfo Uses lines need a fixed register).
• Not entirely sure about putting all tests in features/avr-tiny.ll, but it doesn't seem like the "target-cpu"="attiny10" attribute works.

Patch was based on D138529, but this can be changed easily.

[benshi001]

You can select https://reviews.llvm.org/D138529 as a parent of current patch, then you won't get a patch application failed error.

[benshi001]

llvm/lib/Target/AVR/AVRFrameLowering.cpp

155

I do see avr-gcc save/restore the zero-reg on avrtiny interrupt handlers. Shall we conform with avr-gcc ?

llvm/test/CodeGen/AVR/features/avr-tiny.ll

2

How about also testing atmega328, as a contrast to avrtiny ?

[benshi001]

llvm/test/CodeGen/AVR/features/avr-tiny.ll

60

I do see r17 is pushed/poped by avr-gcc in this case.

// avr-gcc test.c -O3 -Wall -mmcu=attiny10

#include <avr/interrupt.h>

void foo(void);

ISR(BADISR_vect)
{
        foo();
}

[aykevl]

• fix zero register save/restore in interrupts
• also test on atmega328p

[aykevl]

• add explicit zero register to NEGW and ROLB

[aykevl]

I have updated the patch. You are correct about the zero register in interrupts, I must have incorrectly remembered the other behavior. Unfortunately, fixing that also meant changing NEGW and ROLB.
I still think it should be safe to omit saving/restoring R17 but I might do that in a separate patch.

[benshi001]

LGTM. Thanks.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

 
 private:
   typedef MachineBasicBlock Block;
   typedef Block::iterator BlockIt;
 
   const AVRRegisterInfo *TRI;
   const TargetInstrInfo *TII;
 
-  /// The register to be used for temporary storage.
-  const Register SCRATCH_REGISTER = AVR::R0;
-  /// The register that will always contain zero.
-  const Register ZERO_REGISTER = AVR::R1;
-
   bool expandMBB(Block &MBB);
   bool expandMI(Block &MBB, BlockIt MBBI);
   template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
 
   MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
     return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
   }
 
if (ImpIsDead)
     MIBHI->getOperand(2).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
buildMI(MBB, MBBI, AVR::NEGRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstLoReg, getKillRegState(DstIsKill));
 
   // Do an extra SBC.
   auto MISBCI =
       buildMI(MBB, MBBI, AVR::SBCRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
-          .addReg(ZERO_REGISTER);
+          .addReg(STI.getZeroRegister());
   if (ImpIsDead)
     MISBCI->getOperand(3).setIsDead();
   // SREG is always implicitly killed
   MISBCI->getOperand(4).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }

 
 template <typename Func>
 bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
   MachineInstr &MI = *MBBI;
   const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
 
   // Store the SREG.
   buildMI(MBB, MBBI, AVR::INRdA)
-      .addReg(SCRATCH_REGISTER, RegState::Define)
+      .addReg(STI.getTmpRegister(), RegState::Define)
       .addImm(STI.getIORegSREG());
 
   // Disable exceptions.
   buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
 
   f(MI);
 
   // Restore the status reg.
   buildMI(MBB, MBBI, AVR::OUTARr)
       .addImm(STI.getIORegSREG())
-      .addReg(SCRATCH_REGISTER);
+      .addReg(STI.getTmpRegister());
 
   MI.eraseFromParent();
   return true;
 }
 
 template <typename Func>
 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
                                            BlockIt MBBI, Func f) {

 template <>
 bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
   // In AVR, the rotate instructions behave quite unintuitively. They rotate
   // bits through the carry bit in SREG, effectively rotating over 9 bits,
   // instead of 8. This is useful when we are dealing with numbers over
   // multiple registers, but when we actually need to rotate stuff, we have
   // to explicitly add the carry bit.
 
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
   MachineInstr &MI = *MBBI;
   unsigned OpShift, OpCarry;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   OpShift = AVR::ADDRdRr;
   OpCarry = AVR::ADCRdRr;
 
   // add r16, r16
   // adc r16, r1
 
   // Shift part
   buildMI(MBB, MBBI, OpShift)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, RegState::Kill)
       .addReg(DstReg, RegState::Kill);
 
   // Add the carry bit
   auto MIB = buildMI(MBB, MBBI, OpCarry)
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
                  .addReg(DstReg, getKillRegState(DstIsKill))
-                 .addReg(ZERO_REGISTER);
+                 .addReg(STI.getZeroRegister());
 
   MIB->getOperand(3).setIsDead(); // SREG is always dead
   MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
 
   MI.eraseFromParent();
   return true;
 }
 
bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register SrcLoReg, SrcHiReg;
   Register SrcReg = MI.getOperand(1).getReg();
   bool SrcIsKill = MI.getOperand(1).isKill();
   unsigned Flags = MI.getFlags();
   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
   buildMI(MBB, MBBI, AVR::INRdA)
-      .addReg(AVR::R0, RegState::Define)
+      .addReg(STI.getTmpRegister(), RegState::Define)
       .addImm(STI.getIORegSREG())
       .setMIFlags(Flags);
 
   buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
 
   buildMI(MBB, MBBI, AVR::OUTARr)
       .addImm(0x3e)
       .addReg(SrcHiReg, getKillRegState(SrcIsKill))
       .setMIFlags(Flags);
 
   buildMI(MBB, MBBI, AVR::OUTARr)
       .addImm(STI.getIORegSREG())
-      .addReg(AVR::R0, RegState::Kill)
+      .addReg(STI.getTmpRegister(), RegState::Kill)
       .setMIFlags(Flags);
 
   buildMI(MBB, MBBI, AVR::OUTARr)
       .addImm(0x3d)
       .addReg(SrcLoReg, getKillRegState(SrcIsKill))
       .setMIFlags(Flags);
 
   MI.eraseFromParent();

llvm/lib/Target/AVR/AVRFrameLowering.cpp

BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
         .addImm(0x07)
         .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
   // handlers before saving any other registers.
   if (AFI->isInterruptOrSignalHandler()) {
     BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
-        .addReg(AVR::R0, RegState::Kill)
+        .addReg(STI.getTmpRegister(), RegState::Kill)
         .setMIFlag(MachineInstr::FrameSetup);
 
-    BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
+    BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister())
         .addImm(STI.getIORegSREG())
         .setMIFlag(MachineInstr::FrameSetup);
     BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
-        .addReg(AVR::R0, RegState::Kill)
+        .addReg(STI.getTmpRegister(), RegState::Kill)
         .setMIFlag(MachineInstr::FrameSetup);
-    if (!MRI.reg_empty(AVR::R1)) {
+    if (!STI.hasTinyEncoding() && !MRI.reg_empty(STI.getZeroRegister())) {
+      // Saving and zeroing the zero register is needed on non-avrtiny chips
+      // because the mul instruction might destroy it. On avrtiny chips, the
+      // fixed zero register is never modified.
       BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
-          .addReg(AVR::R1, RegState::Kill)
+          .addReg(STI.getZeroRegister(), RegState::Kill)
           .setMIFlag(MachineInstr::FrameSetup);
       BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
-          .addReg(AVR::R1, RegState::Define)
-          .addReg(AVR::R1, RegState::Kill)
-          .addReg(AVR::R1, RegState::Kill)
+          .addReg(STI.getZeroRegister(), RegState::Define)
+          .addReg(STI.getZeroRegister(), RegState::Kill)
+          .addReg(STI.getZeroRegister(), RegState::Kill)
           .setMIFlag(MachineInstr::FrameSetup);
     }
   }
 
   // Early exit if the frame pointer is not needed in this function.
   if (!HasFP) {
     return;
   }
static void restoreStatusRegister(MachineFunction &MF, MachineBasicBlock &MBB) {
 
   DebugLoc DL = MBBI->getDebugLoc();
   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
   const AVRInstrInfo &TII = *STI.getInstrInfo();
 
   // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
   // handlers at the very end of the function, just before reti.
   if (AFI->isInterruptOrSignalHandler()) {
-    if (!MRI.reg_empty(AVR::R1)) {
-      BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R1);
+    if (!STI.hasTinyEncoding() && !MRI.reg_empty(STI.getZeroRegister())) {
+      // See emitPrologue: this is only needed on non-avrtiny chips.
+      BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getZeroRegister());
     }
-    BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
+    BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getTmpRegister());
     BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
         .addImm(STI.getIORegSREG())
-        .addReg(AVR::R0, RegState::Kill);
-    BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
+        .addReg(STI.getTmpRegister(), RegState::Kill);
+    BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getTmpRegister());
   }
 }
 
 void AVRFrameLowering::emitEpilogue(MachineFunction &MF,
                                     MachineBasicBlock &MBB) const {
   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
 
   // Early exit if the frame pointer is not needed in this function except for

llvm/lib/Target/AVR/AVRISelLowering.h

 protected:
   const AVRSubtarget &Subtarget;
 
 private:
   MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
   MachineBasicBlock *insertWideShift(MachineInstr &MI,
                                      MachineBasicBlock *BB) const;
   MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
-  MachineBasicBlock *insertCopyR1(MachineInstr &MI,
+  MachineBasicBlock *insertCopyZero(MachineInstr &MI,
                                     MachineBasicBlock *BB) const;
   MachineBasicBlock *insertAtomicArithmeticOp(MachineInstr &MI,
                                               MachineBasicBlock *BB,
                                               unsigned Opcode, int Width) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_ISEL_LOWERING_H

llvm/lib/Target/AVR/AVRISelLowering.cpp

SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
   // Vastart just stores the address of the VarArgsFrameIndex slot into the
   // memory location argument.
   SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
 
   return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
                       MachinePointerInfo(SV));
 }
 
-// Modify the existing ISD::INLINEASM node to add the implicit register r1.
+// Modify the existing ISD::INLINEASM node to add the implicit zero register.
 SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
-  SDValue R1Reg = DAG.getRegister(AVR::R1, MVT::i8);
-  if (Op.getOperand(Op.getNumOperands() - 1) == R1Reg ||
-      Op.getOperand(Op.getNumOperands() - 2) == R1Reg) {
-    // R1 has already been added. Don't add it again.
+  SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
+  if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg ||
+      Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) {
+    // Zero register has already been added. Don't add it again.
     // If this isn't handled, we get called over and over again.
     return Op;
   }
 
   // Get a list of operands to the new INLINEASM node. This is mostly a copy,
   // with some edits.
   // Add the following operands at the end (but before the glue node, if it's
   // there):
-  //  - The flags of the implicit R1 register operand.
-  //  - The implicit R1 register operand itself.
+  //  - The flags of the implicit zero register operand.
+  //  - The implicit zero register operand itself.
   SDLoc dl(Op);
   SmallVector<SDValue, 8> Ops;
   SDNode *N = Op.getNode();
   SDValue Glue;
   for (unsigned I = 0; I < N->getNumOperands(); I++) {
     SDValue Operand = N->getOperand(I);
     if (Operand.getValueType() == MVT::Glue) {
       // The glue operand always needs to be at the end, so we need to treat it
       // specially.
       Glue = Operand;
     } else {
       Ops.push_back(Operand);
     }
   }
   unsigned Flags = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
   Ops.push_back(DAG.getTargetConstant(Flags, dl, MVT::i32));
-  Ops.push_back(R1Reg);
+  Ops.push_back(ZeroReg);
   if (Glue) {
     Ops.push_back(Glue);
   }
 
-  // Replace the current INLINEASM node with a new one that has R1 as implicit
-  // parameter.
+  // Replace the current INLINEASM node with a new one that has the zero
+  // register as implicit parameter.
   SDValue New = DAG.getNode(N->getOpcode(), dl, N->getVTList(), Ops);
   DAG.ReplaceAllUsesOfValueWith(Op, New);
   DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), New.getValue(1));
 
   return New;
 }
 
 SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   Ops.push_back(Callee);
 
   // Add argument registers to the end of the list so that they are known live
   // into the call.
   for (auto Reg : RegsToPass) {
     Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
   }
 
-  // The R1 register must be passed as an implicit register so that R1 is
-  // correctly zeroed in interrupts.
-  Ops.push_back(DAG.getRegister(AVR::R1, MVT::i8));
+  // The zero register (usually R1) must be passed as an implicit register so
+  // that this register is correctly zeroed in interrupts.
+  Ops.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8));
 
   // Add a register mask operand representing the call-preserved registers.
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   const uint32_t *Mask =
       TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
   assert(Mask && "Missing call preserved mask for calling convention");
   Ops.push_back(DAG.getRegisterMask(Mask));
 
AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
   // the function being compiled.
   if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
     return Chain;
   }
 
   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
 
   if (!AFI->isInterruptOrSignalHandler()) {
-    // The return instruction has an implicit R1 operand: it must contain zero
-    // on return.
-    // This is not needed in interrupts however, where R1 is handled specially
-    // (only pushed/popped when needed).
-    RetOps.push_back(DAG.getRegister(AVR::R1, MVT::i8));
+    // The return instruction has an implicit zero register operand: it must
+    // contain zero on return.
+    // This is not needed in interrupts however, where the zero register is
+    // handled specially (only pushed/popped when needed).
+    RetOps.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8));
   }
 
   unsigned RetOpc =
       AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
 
   RetOps[0] = Chain; // Update chain.
 
   if (Flag.getNode()) {

 // algorithms have to work independently of the number of registers that are
 // shifted.
 // For more information and background, see this blogpost:
 // https://aykevl.nl/2021/02/avr-bitshift
 static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
                                  MutableArrayRef<std::pair<Register, int>> Regs,
                                  int64_t ShiftAmt, bool ArithmeticShift) {
   const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
+  const AVRSubtarget &STI = BB->getParent()->getSubtarget<AVRSubtarget>();
   MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
   DebugLoc dl = MI.getDebugLoc();
 
   // Do a shift modulo 6 or 7. This is a bit more complicated than most shifts
   // and is hard to compose with the rest, so these are special cased.
   // The basic idea is to shift one or two bits in the opposite direction and
   // then move registers around to get the correct end result.
   if (ShiftAmt < 0 && (-ShiftAmt % 8) >= 6) {
     // Left shift modulo 6 or 7.
 
     // Create a slice of the registers we're going to modify, to ease working
     // with them.
     size_t ShiftRegsOffset = -ShiftAmt / 8;
     size_t ShiftBytes = Regs.size() - ShiftRegsOffset;
     MutableArrayRef<std::pair<Register, int>> ShiftRegs =
         Regs.slice(ShiftRegsOffset, ShiftBytes);
 
     // Shift one to the right, keeping the least significant bit as the carry
     // bit.
     insertMultibyteShift(MI, BB, ShiftRegs, 1, false);
 
     // Create zero register.
     Register Zero = MRI.createVirtualRegister(&AVR::GPR8RegClass);
-    BuildMI(*BB, MI, dl, TII.get(AVR::COPY), Zero).addReg(AVR::R1);
+    BuildMI(*BB, MI, dl, TII.get(AVR::COPY), Zero)
+        .addReg(STI.getZeroRegister());
 
     // Rotate the least significant bit from the carry bit into a new register
     // (that starts out zero).
     Register LowByte = MRI.createVirtualRegister(&AVR::GPR8RegClass);
     BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(Zero);
 
     // Shift one more to the right if this is a modulo-6 shift.
     if (-ShiftAmt % 8 == 6) {
if (ArithmeticShift) {
       // Sign-extend bit that was shifted out last.
       BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), Ext)
           .addReg(Ext, RegState::Undef)
           .addReg(Ext, RegState::Undef);
       ExtMore = Ext;
     } else {
       // Create a new zero register for zero extending.
       ExtMore = MRI.createVirtualRegister(&AVR::GPR8RegClass);
-      BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ExtMore).addReg(AVR::R1);
+      BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ExtMore)
+          .addReg(STI.getZeroRegister());
       // Rotate most significant bit into a new register (that starts out zero).
       BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), Ext)
           .addReg(ExtMore)
           .addReg(ExtMore);
     }
 
     // Shift one more to the left for modulo 6 shifts.
     if (ShiftAmt % 8 == 6) {
static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
   while (ShiftAmt <= -8) {
     // Move all registers one to the left.
     for (size_t I = 0; I < Regs.size() - 1; I++) {
       Regs[I] = Regs[I + 1];
     }
 
     // Zero the least significant register.
     Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass);
-    BuildMI(*BB, MI, dl, TII.get(AVR::COPY), Out).addReg(AVR::R1);
+    BuildMI(*BB, MI, dl, TII.get(AVR::COPY), Out).addReg(STI.getZeroRegister());
     Regs[Regs.size() - 1] = std::pair(Out, 0);
 
     // Continue shifts with the leftover registers.
     Regs = Regs.slice(0, Regs.size() - 1);
 
     ShiftAmt += 8;
   }
   while (ShiftAmt >= 8) {
if (ShrExtendReg == 0) {
         Register Tmp = MRI.createVirtualRegister(&AVR::GPR8RegClass);
         BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Tmp)
             .addReg(MSBReg.first, 0, MSBReg.second)
             .addReg(MSBReg.first, 0, MSBReg.second);
         BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), ShrExtendReg)
             .addReg(Tmp)
             .addReg(Tmp);
       } else {
-        BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ShrExtendReg).addReg(AVR::R1);
+        BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ShrExtendReg)
+            .addReg(STI.getZeroRegister());
       }
     }
     Regs[0] = std::pair(ShrExtendReg, 0);
 
     // Continue shifts with the leftover registers.
     Regs = Regs.slice(1, Regs.size() - 1);
 
     ShiftAmt -= 8;
MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
   if (isCopyMulResult(I))
     ++I;
   BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
       .addReg(AVR::R1)
       .addReg(AVR::R1);
   return BB;
 }
 
-// Insert a read from R1, which almost always contains the value 0.
+// Insert a read from the zero register.
 MachineBasicBlock *
-AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const {
+AVRTargetLowering::insertCopyZero(MachineInstr &MI,
+                                  MachineBasicBlock *BB) const {
   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
   MachineBasicBlock::iterator I(MI);
   BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
       .add(MI.getOperand(0))
-      .addReg(AVR::R1);
+      .addReg(Subtarget.getZeroRegister());
   MI.eraseFromParent();
   return BB;
 }
 
 // Lower atomicrmw operation to disable interrupts, do operation, and restore
 // interrupts. This works because all AVR microcontrollers are single core.
 MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
     MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
   MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
   MachineBasicBlock::iterator I(MI);
-  const Register SCRATCH_REGISTER = AVR::R0;
   DebugLoc dl = MI.getDebugLoc();
 
   // Example instruction sequence, for an atomic 8-bit add:
   //   ldi r25, 5
   //   in r0, SREG
   //   cli
   //   ld r24, X
   //   add r25, r24
   //   st X, r25
   //   out SREG, r0
 
   const TargetRegisterClass *RC =
       (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
   unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
   unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
 
   // Disable interrupts.
-  BuildMI(*BB, I, dl, TII.get(AVR::INRdA), SCRATCH_REGISTER)
+  BuildMI(*BB, I, dl, TII.get(AVR::INRdA), Subtarget.getTmpRegister())
       .addImm(Subtarget.getIORegSREG());
   BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7);
 
   // Load the original value.
   BuildMI(*BB, I, dl, TII.get(LoadOpcode), MI.getOperand(0).getReg())
       .add(MI.getOperand(1));
 
   // Do the arithmetic operation.
   Register Result = MRI.createVirtualRegister(RC);
   BuildMI(*BB, I, dl, TII.get(Opcode), Result)
       .addReg(MI.getOperand(0).getReg())
       .add(MI.getOperand(2));
 
   // Store the result.
   BuildMI(*BB, I, dl, TII.get(StoreOpcode))
       .add(MI.getOperand(1))
       .addReg(Result);
 
   // Restore interrupts.
   BuildMI(*BB, I, dl, TII.get(AVR::OUTARr))
       .addImm(Subtarget.getIORegSREG())
-      .addReg(SCRATCH_REGISTER);
+      .addReg(Subtarget.getTmpRegister());
 
   // Remove the pseudo instruction.
   MI.eraseFromParent();
   return BB;
 }
 
 MachineBasicBlock *
 AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case AVR::Asr16:
     return insertShift(MI, MBB);
   case AVR::Lsl32:
   case AVR::Lsr32:
   case AVR::Asr32:
     return insertWideShift(MI, MBB);
   case AVR::MULRdRr:
   case AVR::MULSRdRr:
     return insertMul(MI, MBB);
-  case AVR::CopyR1:
-    return insertCopyR1(MI, MBB);
+  case AVR::CopyZero:
+    return insertCopyZero(MI, MBB);
   case AVR::AtomicLoadAdd8:
     return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8);
   case AVR::AtomicLoadAdd16:
     return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16);
   case AVR::AtomicLoadSub8:
     return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8);
   case AVR::AtomicLoadSub16:
     return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16);
if (Constraint.size() == 1) {
     case 'r': // Any register: r0..r31.
       if (VT == MVT::i8)
         return std::make_pair(0U, &AVR::GPR8RegClass);
       else if (VT == MVT::i16)
         return std::make_pair(0U, &AVR::DREGSRegClass);
       break;
     case 't': // Temporary register: r0.
       if (VT == MVT::i8)
-        return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
+        return std::make_pair(unsigned(Subtarget.getTmpRegister()),
+                              &AVR::GPR8RegClass);
       break;
     case 'w': // Special upper register pairs: r24, r26, r28, r30.
       if (VT == MVT::i8 || VT == MVT::i16)
         return std::make_pair(0U, &AVR::IWREGSRegClass);
       break;
     case 'x': // Pointer register pair X: r27:r26.
     case 'X':
       if (VT == MVT::i8 || VT == MVT::i16)

llvm/lib/Target/AVR/AVRInstrInfo.td

def NEGRd
                          (implicit SREG)]>;
 
   // NEGW Rd+1:Rd
   //
   // Expands to:
   // neg Rd+1
   // neg Rd
   // sbc Rd+1, r1
+  //
+  // Note: this pseudo instruction actually uses R17 on avrtiny.
+  // This is fine, because R17 is never modified on avrtiny.
   let Uses = [R1] in
   def NEGWRd : Pseudo<(outs DREGS
                        : $rd),
                       (ins DREGS
                        : $src),
                       "negw\t$rd",
                       [(set i16
                         : $rd, (ineg i16
def ASRWRd : Pseudo<(outs DREGS
                       [(set i16
                         : $rd, (AVRasr i16
                                 : $src)),
                        (implicit SREG)]>;
 
   def ASRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrwlo\t$rd",
                         [(set i16:$rd, (AVRasrlo i16:$src)), (implicit SREG)]>;
 
+  // Note: this pseudo instruction actually uses R17 on avrtiny.
+  // This is fine, because R17 is never modified on avrtiny.
   let Uses = [R1] in
   def ROLBRd : Pseudo<(outs GPR8
                        : $rd),
                       (ins GPR8
                        : $src),
                       "rolb\t$rd",
                       [(set i8
                         : $rd, (AVRrol i8
def Asr16 : ShiftPseudo<(outs DREGS
                                                      : $src, i8
                                                      : $cnt))]>;
 
 def Asr32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),
                         (ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),
                         "# Asr32 PSEUDO",
                         [(set i16:$dstlo, i16:$dsthi, (AVRasrw i16:$srclo, i16:$srchi, i8:$cnt))]>;
 
-// lowered to a copy from R1, which contains the value zero.
+// lowered to a copy from the zero register.
 let usesCustomInserter=1 in
-def CopyR1 : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;
+def CopyZero : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
 //: TODO: look in x86InstrCompiler.td for odd encoding trick related to
 // add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor)
 

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

if ((Offset - 63 + 1) > 63) {
       SubOpc = AVR::SUBIWRdK;
       AddOffset = -AddOffset;
     }
 
     // It is possible that the spiller places this frame instruction in between
     // a compare and branch, invalidating the contents of SREG set by the
     // compare instruction because of the add/sub pairs. Conservatively save and
     // restore SREG before and after each add/sub pair.
-    BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0)
+    BuildMI(MBB, II, dl, TII.get(AVR::INRdA), STI.getTmpRegister())
         .addImm(STI.getIORegSREG());
 
     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
                             .addReg(AVR::R29R28, RegState::Kill)
                             .addImm(AddOffset);
     New->getOperand(3).setIsDead();
 
     // Restore SREG.
     BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
         .addImm(STI.getIORegSREG())
-        .addReg(AVR::R0, RegState::Kill);
+        .addReg(STI.getTmpRegister(), RegState::Kill);
 
     // No need to set SREG as dead here otherwise if the next instruction is a
     // cond branch it will be using a dead register.
     BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
         .addReg(AVR::R29R28, RegState::Kill)
         .addImm(Offset - 63 + 1);
 
     Offset = 62;

llvm/lib/Target/AVR/AVRSubtarget.h

 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Target/TargetMachine.h"
 
 #include "AVRFrameLowering.h"
 #include "AVRISelLowering.h"
 #include "AVRInstrInfo.h"
 #include "AVRSelectionDAGInfo.h"
+#include "MCTargetDesc/AVRMCTargetDesc.h"
 
 #define GET_SUBTARGETINFO_HEADER
 #include "AVRGenSubtargetInfo.inc"
 
 namespace llvm {
 
 /// A specific AVR target MCU.
 class AVRSubtarget : public AVRGenSubtargetInfo {
public:
   int getIORegSPL() const { return 0x3d; }
   int getIORegSPH() const { return hasSmallStack() ? -1 : 0x3e; }
   int getIORegSREG() const { return 0x3f; }
 
   /// Get GPR aliases.
   int getRegTmpIndex() const { return hasTinyEncoding() ? 16 : 0; }
   int getRegZeroIndex() const { return hasTinyEncoding() ? 17 : 1; }
 
+  Register getTmpRegister() const {
+    return hasTinyEncoding() ? AVR::R16 : AVR::R0;
+  }
+  Register getZeroRegister() const {
+    return hasTinyEncoding() ? AVR::R17 : AVR::R1;
+  }
+
 private:
   /// The ELF e_flags architecture.
   unsigned ELFArch;
 
   // Subtarget feature settings
   // See AVR.td for details.
   bool m_hasSRAM;
   bool m_hasJMPCALL;

llvm/test/CodeGen/AVR/features/avr-tiny.ll

-; RUN: llc -mattr=avrtiny -O0 < %s -march=avr | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mattr=avrtiny -O0 < %s -mtriple=avr | FileCheck %s
 
 define i16 @reg_copy16(i16, i16 %a) {
-; CHECK-LABEL: reg_copy16
-; CHECK: mov r24, r22
-; CHECK: mov r25, r23
-
+; CHECK-LABEL: reg_copy16:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    mov r24, r22
+; CHECK-NEXT:    mov r25, r23
+; CHECK-NEXT:    ret
   ret i16 %a
 }
+
+define i8 @return_zero() {
+; CHECK-LABEL: return_zero:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    mov r24, r17
+; CHECK-NEXT:    ret
+  ret i8 0
+}
+
+define i8 @atomic_load8(i8* %foo) {
+; CHECK-LABEL: atomic_load8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    mov r26, r24
+; CHECK-NEXT:    mov r27, r25
+; CHECK-NEXT:    in r16, 63
+; CHECK-NEXT:    cli
+; CHECK-NEXT:    ld r24, X
+; CHECK-NEXT:    out 63, r16
+; CHECK-NEXT:    ret
+  %val = load atomic i8, i8* %foo unordered, align 1
+  ret i8 %val
+}
+
+define avr_signalcc void @signal_handler_with_asm() {
+; CHECK-LABEL: signal_handler_with_asm:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r16
+; CHECK-NEXT:    in r16, 63
+; CHECK-NEXT:    push r16
+; CHECK-NEXT:    push r24
+; CHECK-NEXT:    ldi r24, 3
+; CHECK-NEXT:    ;APP
+; CHECK-NEXT:    mov r24, r24
+; CHECK-NEXT:    ;NO_APP
+; CHECK-NEXT:    pop r24
+; CHECK-NEXT:    pop r16
+; CHECK-NEXT:    out 63, r16
+; CHECK-NEXT:    pop r16
+; CHECK-NEXT:    reti
+  call i8 asm sideeffect "mov $0, $1", "=r,r"(i8 3) nounwind
+  ret void
+}
+
+declare void @foo()
+
+define avr_signalcc void @signal_handler_with_call() {
+; CHECK-LABEL: signal_handler_with_call:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r16
+; CHECK-NEXT:    in r16, 63
+; CHECK-NEXT:    push r16
+; CHECK-NEXT:    push r20
+; CHECK-NEXT:    push r21
+; CHECK-NEXT:    push r22
+; CHECK-NEXT:    push r23
+; CHECK-NEXT:    push r24
+; CHECK-NEXT:    push r25
+; CHECK-NEXT:    push r26
+; CHECK-NEXT:    push r27
+; CHECK-NEXT:    push r30
+; CHECK-NEXT:    push r31
+; CHECK-NEXT:    rcall foo
+; CHECK-NEXT:    pop r31
+; CHECK-NEXT:    pop r30
+; CHECK-NEXT:    pop r27
+; CHECK-NEXT:    pop r26
+; CHECK-NEXT:    pop r25
+; CHECK-NEXT:    pop r24
+; CHECK-NEXT:    pop r23
+; CHECK-NEXT:    pop r22
+; CHECK-NEXT:    pop r21
+; CHECK-NEXT:    pop r20
+; CHECK-NEXT:    pop r16
+; CHECK-NEXT:    out 63, r16
+; CHECK-NEXT:    pop r16
+; CHECK-NEXT:    reti
+  call void @foo()
+  ret void
+}