[IRCE] Bail out if Start AddRec is for another loop

[dmakogon]

Summary

Imagine we have an outer loop and an inner loop, which is in the outer one, and a range check in outer loop of such addrec:

{{0,+,1}<%outer_header>,+,1}<%inner_header>

When IRCE runs on the outer loop it sees the range check and tries to check whether it is possible to safely calculate the loop bound.
However, this addrec is for the inner loop, so we shouldn't do anything at all.

Fixes https://github.com/llvm/llvm-project/issues/58912

[mkazantsev]

LG with nits.

llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp

849

Looks weird w.r.t. messages right below, better "LHS in cmp is not an AddRec for this loop"

llvm/test/Transforms/IRCE/iv-for-another-loop.ll

2–3

Add new PM.

8

Remove this and auto-generate checks.

[mkazantsev]

Add "PR58912" to commit name.

[dmakogon]

Updated comment and test

llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp

auto HasNoSignedWrap = [&](const SCEVAddRecExpr *AR) {
     // We may have proved this when computing the sign extension above.
     return AR->getNoWrapFlags(SCEV::FlagNSW) != SCEV::FlagAnyWrap;
   };
 
   // `ICI` is interpreted as taking the backedge if the *next* value of the
   // induction variable satisfies some constraint.
 
   const SCEVAddRecExpr *IndVarBase = cast<SCEVAddRecExpr>(LeftSCEV);
+  if (IndVarBase->getLoop() != &L) {
+    FailureReason = "LHS in cmp is not an AddRec for this loop";
+    return None;
+  }
   if (!IndVarBase->isAffine()) {
     FailureReason = "LHS in icmp not induction variable";
     return None;
   }
   const SCEV* StepRec = IndVarBase->getStepRecurrence(SE);
   if (!isa<SCEVConstant>(StepRec)) {
     FailureReason = "LHS in icmp not induction variable";
     return None;

llvm/test/Transforms/IRCE/iv-for-another-loop.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -irce -irce-print-changed-loops=true < %s | FileCheck %s
+; RUN: opt -S -passes=irce -irce-print-changed-loops=true < %s | FileCheck %s
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; REQUIRES: asserts
-; XFAIL: *
 
 define void @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
+; CHECK:       outer_latch:
+; CHECK-NEXT:    [[TMP:%.*]] = or i32 [[TMP5:%.*]], 1
+; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i32 [[TMP5]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP8:%.*]], 0
+; CHECK-NEXT:    br i1 [[TMP3]], label [[RET2:%.*]], label [[OUTER_HEADER]]
+; CHECK:       outer_header:
+; CHECK-NEXT:    [[TMP5]] = phi i32 [ 0, [[BB:%.*]] ], [ [[TMP2]], [[OUTER_LATCH:%.*]] ]
+; CHECK-NEXT:    br label [[INNER_HEADER:%.*]]
+; CHECK:       inner_exit:
+; CHECK-NEXT:    [[TMP12_LCSSA:%.*]] = phi i32 [ [[TMP12:%.*]], [[INNER_HEADER]] ]
+; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP12_LCSSA]], [[TMP5]]
+; CHECK-NEXT:    [[TMP8]] = add nuw i32 [[TMP12_LCSSA]], [[TMP5]]
+; CHECK-NEXT:    [[TMP9:%.*]] = icmp ult i32 [[TMP5]], 0
+; CHECK-NEXT:    br i1 [[TMP9]], label [[OUTER_LATCH]], label [[RET1:%.*]]
+; CHECK:       ret1:
+; CHECK-NEXT:    ret void
+; CHECK:       inner_header:
+; CHECK-NEXT:    [[TMP12]] = phi i32 [ [[TMP14:%.*]], [[INNER_HEADER]] ], [ 0, [[OUTER_HEADER]] ]
+; CHECK-NEXT:    [[TMP13:%.*]] = or i32 [[TMP12]], 1
+; CHECK-NEXT:    [[TMP14]] = add nuw nsw i32 [[TMP12]], 1
+; CHECK-NEXT:    br i1 true, label [[INNER_EXIT:%.*]], label [[INNER_HEADER]]
+; CHECK:       ret2:
+; CHECK-NEXT:    ret void
+;
 bb:
   br label %outer_header
 
 outer_latch:                                      ; preds = %inner_exit
   %tmp = or i32 %tmp5, 1
   %tmp2 = add nuw nsw i32 %tmp5, 1
   %tmp3 = icmp eq i32 %tmp8, 0
   br i1 %tmp3, label %ret2, label %outer_header