[AMDGPU] Select S_LSHR_B64 for uniform fshr

[foad]

Work in progress. I need to think about the regressions and check what globalisel is doing.

llvm/lib/Target/AMDGPU/SIInstructions.td

def : AMDGPUPat <
   (fcopysign f64:$src0, f32:$src1),
   (REG_SEQUENCE SReg_64,
     (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
     (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)),
                (i32 (EXTRACT_SUBREG SReg_64:$src0, sub1)),
                $src1), sub1)
 >;
 
+def : GCNPat<
+  (UniformTernaryFrag<fshr> i32:$src0, i32:$src1, i32:$src2),
+  (EXTRACT_SUBREG (S_LSHR_B64 (REG_SEQUENCE SReg_64, $src1, sub0, $src0, sub1), $src2), sub0)
+>;
+
 def : ROTRPattern <V_ALIGNBIT_B32_e64>;
 
 def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
           (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
                           (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
 
 def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
           (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),

llvm/lib/Target/AMDGPU/SOPInstructions.td

class UniformBinFrag<SDPatternOperator Op> : PatFrag <
   // This check is unnecessary as it's captured by the result register
   // bank constraint.
   //
   // FIXME: Should add a way for the emitter to recognize this is a
   // trivially true predicate to eliminate the check.
   let GISelPredicateCode = [{return true;}];
 }
 
+class UniformTernaryFrag<SDPatternOperator Op> : PatFrag <
+  (ops node:$src0, node:$src1, node:$src2),
+  (Op $src0, $src1, $src2),
+  [{ return !N->isDivergent(); }]> {
+  // This check is unnecessary as it's captured by the result register
+  // bank constraint.
+  //
+  // FIXME: Should add a way for the emitter to recognize this is a
+  // trivially true predicate to eliminate the check.
+  let GISelPredicateCode = [{return true;}];
+}
+
 class DivergentBinFrag<SDPatternOperator Op> : PatFrag <
   (ops node:$src0, node:$src1),
   (Op $src0, $src1),
   [{ return N->isDivergent(); }]> {
   // This check is unnecessary as it's captured by the result register
   // bank constraint.
   //
   // FIXME: Should add a way for the emitter to recognize this is a

llvm/test/CodeGen/AMDGPU/fshl.ll

 define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %z) {
 ; SI-LABEL: fshl_i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; SI-NEXT:    s_load_dword s8, s[0:1], 0xd
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s1, s5
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    s_not_b32 s5, s8
 ; SI-NEXT:    s_mov_b32 s0, s4
-; SI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; SI-NEXT:    s_lshr_b32 s4, s6, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s5
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v1
+; SI-NEXT:    s_mov_b32 s1, s5
+; SI-NEXT:    s_mov_b32 s4, s7
+; SI-NEXT:    s_mov_b32 s5, s6
+; SI-NEXT:    s_lshr_b32 s9, s6, 1
+; SI-NEXT:    s_lshr_b64 s[4:5], s[4:5], 1
+; SI-NEXT:    s_mov_b32 s5, s9
+; SI-NEXT:    s_not_b32 s6, s8
+; SI-NEXT:    s_lshr_b64 s[4:5], s[4:5], s6
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT:    s_load_dword s0, s[0:1], 0x34
+; VI-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    s_not_b32 s0, s0
-; VI-NEXT:    s_lshr_b32 s1, s6, 1
-; VI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s0
-; VI-NEXT:    v_alignbit_b32 v2, s1, v0, v1
+; VI-NEXT:    s_mov_b32 s0, s7
+; VI-NEXT:    s_mov_b32 s1, s6
+; VI-NEXT:    s_lshr_b32 s3, s6, 1
+; VI-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
+; VI-NEXT:    s_not_b32 s2, s2
+; VI-NEXT:    s_mov_b32 s1, s3
+; VI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s7
-; GFX9-NEXT:    s_not_b32 s1, s2
-; GFX9-NEXT:    s_lshr_b32 s0, s6, 1
-; GFX9-NEXT:    v_alignbit_b32 v1, s6, v1, 1
-; GFX9-NEXT:    v_mov_b32_e32 v2, s1
-; GFX9-NEXT:    v_alignbit_b32 v1, s0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s0, s7
+; GFX9-NEXT:    s_mov_b32 s1, s6
+; GFX9-NEXT:    s_lshr_b32 s3, s6, 1
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
+; GFX9-NEXT:    s_mov_b32 s1, s3
+; GFX9-NEXT:    s_not_b32 s2, s2
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_i32:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     LSHR T0.Z, KC0[2].Z, 1,
 ; R600-NEXT:     BIT_ALIGN_INT T0.W, KC0[2].Z, KC0[2].W, 1,
 ; R600-NEXT:     NOT_INT * T1.W, KC0[3].X,
 ; R600-NEXT:     BIT_ALIGN_INT T0.X, PV.Z, PV.W, PS,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX10-NEXT:    s_load_dword s2, s[0:1], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
+; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v0, s6, s7, 1
-; GFX10-NEXT:    s_lshr_b32 s0, s6, 1
-; GFX10-NEXT:    s_not_b32 s1, s2
-; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, s1
-; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]
+; GFX10-NEXT:    s_mov_b32 s0, s7
+; GFX10-NEXT:    s_mov_b32 s1, s6
+; GFX10-NEXT:    s_lshr_b32 s3, s6, 1
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
+; GFX10-NEXT:    s_mov_b32 s1, s3
+; GFX10-NEXT:    s_not_b32 s2, s2
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-NEXT:    s_load_b32 s2, s[0:1], 0x34
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, s6, s7, 1
-; GFX11-NEXT:    s_lshr_b32 s1, s6, 1
-; GFX11-NEXT:    s_not_b32 s0, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s1, v0, s0
-; GFX11-NEXT:    global_store_b32 v1, v0, s[4:5]
+; GFX11-NEXT:    s_mov_b32 s0, s7
+; GFX11-NEXT:    s_mov_b32 s1, s6
+; GFX11-NEXT:    s_lshr_b32 s3, s6, 1
+; GFX11-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
+; GFX11-NEXT:    s_mov_b32 s1, s3
+; GFX11-NEXT:    s_not_b32 s2, s2
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT:    global_store_b32 v0, v1, s[4:5]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
   store i32 %0, i32 addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_i32_imm(i32 addrspace(1)* %in, i32 %x, i32 %y) {
 ; SI-LABEL: fshl_i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s3
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
-; SI-NEXT:    v_alignbit_b32 v0, s2, v0, 25
+; SI-NEXT:    s_mov_b32 s0, s3
+; SI-NEXT:    s_mov_b32 s1, s2
+; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], 25
+; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_alignbit_b32 v2, s2, v0, 25
+; VI-NEXT:    s_mov_b32 s4, s3
+; VI-NEXT:    s_mov_b32 s5, s2
+; VI-NEXT:    s_lshr_b64 s[2:3], s[4:5], 25
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_alignbit_b32 v1, s2, v1, 25
+; GFX9-NEXT:    s_mov_b32 s4, s3
+; GFX9-NEXT:    s_mov_b32 s5, s2
+; GFX9-NEXT:    s_lshr_b64 s[2:3], s[4:5], 25
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_i32_imm:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
 ; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s2, s3, 25
+; GFX10-NEXT:    s_mov_b32 s4, s3
+; GFX10-NEXT:    s_mov_b32 s5, s2
+; GFX10-NEXT:    s_lshr_b64 s[2:3], s[4:5], 25
+; GFX10-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s2, s3, 25
+; GFX11-NEXT:    s_mov_b32 s4, s3
+; GFX11-NEXT:    s_mov_b32 s5, s2
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[4:5], 25
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
 ; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7)
   store i32 %0, i32 addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; SI-LABEL: fshl_v2i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xf
 ; SI-NEXT:    s_mov_b32 s11, 0xf000
 ; SI-NEXT:    s_mov_b32 s10, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
+; SI-NEXT:    s_mov_b32 s2, s7
+; SI-NEXT:    s_mov_b32 s3, s5
+; SI-NEXT:    s_lshr_b32 s12, s5, 1
+; SI-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
+; SI-NEXT:    s_mov_b32 s3, s12
 ; SI-NEXT:    s_not_b32 s1, s1
-; SI-NEXT:    s_lshr_b32 s2, s5, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s1
-; SI-NEXT:    v_alignbit_b32 v1, s2, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s6
-; SI-NEXT:    s_not_b32 s0, s0
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
+; SI-NEXT:    s_mov_b32 s7, s4
+; SI-NEXT:    s_lshr_b64 s[2:3], s[2:3], s1
 ; SI-NEXT:    s_lshr_b32 s1, s4, 1
-; SI-NEXT:    v_mov_b32_e32 v2, s0
-; SI-NEXT:    v_alignbit_b32 v0, s1, v0, v2
+; SI-NEXT:    s_lshr_b64 s[4:5], s[6:7], 1
+; SI-NEXT:    s_mov_b32 s5, s1
+; SI-NEXT:    s_not_b32 s0, s0
+; SI-NEXT:    s_lshr_b64 s[0:1], s[4:5], s0
+; SI-NEXT:    v_mov_b32_e32 v0, s0
+; SI-NEXT:    v_mov_b32_e32 v1, s2
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v2i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    s_not_b32 s3, s3
-; VI-NEXT:    s_lshr_b32 s7, s5, 1
-; VI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v1, s7, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s6
-; VI-NEXT:    s_not_b32 s2, s2
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; VI-NEXT:    s_lshr_b32 s3, s4, 1
+; VI-NEXT:    s_mov_b32 s8, s7
+; VI-NEXT:    s_mov_b32 s9, s5
+; VI-NEXT:    s_lshr_b32 s10, s5, 1
+; VI-NEXT:    s_lshr_b64 s[8:9], s[8:9], 1
+; VI-NEXT:    s_mov_b32 s9, s10
+; VI-NEXT:    s_not_b32 s1, s1
+; VI-NEXT:    s_mov_b32 s7, s4
+; VI-NEXT:    s_lshr_b64 s[8:9], s[8:9], s1
+; VI-NEXT:    s_lshr_b32 s1, s4, 1
+; VI-NEXT:    s_lshr_b64 s[4:5], s[6:7], 1
+; VI-NEXT:    s_mov_b32 s5, s1
+; VI-NEXT:    s_not_b32 s0, s0
+; VI-NEXT:    s_lshr_b64 s[0:1], s[4:5], s0
 ; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_alignbit_b32 v0, s3, v0, v2
-; VI-NEXT:    v_mov_b32_e32 v3, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s8
+; VI-NEXT:    v_mov_b32_e32 v3, s3
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v2i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x3c
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    s_lshr_b32 s0, s5, 1
-; GFX9-NEXT:    s_not_b32 s1, s9
-; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v1, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s6
-; GFX9-NEXT:    s_not_b32 s1, s8
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s4, 1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s1
-; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v3
+; GFX9-NEXT:    s_mov_b32 s8, s7
+; GFX9-NEXT:    s_mov_b32 s9, s5
+; GFX9-NEXT:    s_lshr_b32 s10, s5, 1
+; GFX9-NEXT:    s_lshr_b64 s[8:9], s[8:9], 1
+; GFX9-NEXT:    s_mov_b32 s9, s10
+; GFX9-NEXT:    s_not_b32 s1, s1
+; GFX9-NEXT:    s_mov_b32 s7, s4
+; GFX9-NEXT:    s_lshr_b64 s[8:9], s[8:9], s1
+; GFX9-NEXT:    s_lshr_b32 s1, s4, 1
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], 1
+; GFX9-NEXT:    s_mov_b32 s5, s1
+; GFX9-NEXT:    s_not_b32 s0, s0
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[4:5], s0
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s8
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v2i32:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END

 ; GFX10-LABEL: fshl_v2i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x2
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX10-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v0, s5, s7, 1
-; GFX10-NEXT:    v_alignbit_b32 v3, s4, s6, 1
-; GFX10-NEXT:    s_lshr_b32 s0, s5, 1
-; GFX10-NEXT:    s_not_b32 s1, s3
-; GFX10-NEXT:    s_lshr_b32 s3, s4, 1
-; GFX10-NEXT:    s_not_b32 s2, s2
-; GFX10-NEXT:    v_alignbit_b32 v1, s0, v0, s1
-; GFX10-NEXT:    v_alignbit_b32 v0, s3, v3, s2
+; GFX10-NEXT:    s_mov_b32 s0, s7
+; GFX10-NEXT:    s_mov_b32 s1, s5
+; GFX10-NEXT:    s_mov_b32 s7, s4
+; GFX10-NEXT:    s_lshr_b32 s10, s5, 1
+; GFX10-NEXT:    s_lshr_b32 s11, s4, 1
+; GFX10-NEXT:    s_not_b32 s5, s3
+; GFX10-NEXT:    s_not_b32 s4, s2
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
+; GFX10-NEXT:    s_lshr_b64 s[2:3], s[6:7], 1
+; GFX10-NEXT:    s_mov_b32 s3, s11
+; GFX10-NEXT:    s_mov_b32 s1, s10
+; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s4
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s5
+; GFX10-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v2i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
 ; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x3c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, s5, s7, 1
-; GFX11-NEXT:    v_alignbit_b32 v3, s4, s6, 1
-; GFX11-NEXT:    s_lshr_b32 s5, s5, 1
-; GFX11-NEXT:    s_not_b32 s3, s3
-; GFX11-NEXT:    s_lshr_b32 s4, s4, 1
-; GFX11-NEXT:    s_not_b32 s2, s2
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, v0, s3
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, v3, s2
+; GFX11-NEXT:    s_mov_b32 s8, s7
+; GFX11-NEXT:    s_mov_b32 s9, s5
+; GFX11-NEXT:    s_mov_b32 s7, s4
+; GFX11-NEXT:    s_lshr_b32 s10, s5, 1
+; GFX11-NEXT:    s_lshr_b32 s12, s4, 1
+; GFX11-NEXT:    s_not_b32 s11, s3
+; GFX11-NEXT:    s_not_b32 s13, s2
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[8:9], 1
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[6:7], 1
+; GFX11-NEXT:    s_mov_b32 s5, s12
+; GFX11-NEXT:    s_mov_b32 s3, s10
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[4:5], s13
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], s11
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
   store <2 x i32> %0, <2 x i32> addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
 ; SI-LABEL: fshl_v2i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v2, s6
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 23
-; SI-NEXT:    v_alignbit_b32 v0, s4, v2, 25
+; SI-NEXT:    s_mov_b32 s8, s7
+; SI-NEXT:    s_mov_b32 s9, s5
+; SI-NEXT:    s_mov_b32 s7, s4
+; SI-NEXT:    s_lshr_b64 s[8:9], s[8:9], 23
+; SI-NEXT:    s_lshr_b64 s[4:5], s[6:7], 25
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s8
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v2i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v2, s6
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 23
-; VI-NEXT:    v_alignbit_b32 v0, s4, v2, 25
+; VI-NEXT:    s_mov_b32 s2, s7
+; VI-NEXT:    s_mov_b32 s3, s5
+; VI-NEXT:    s_mov_b32 s7, s4
+; VI-NEXT:    s_lshr_b64 s[2:3], s[2:3], 23
+; VI-NEXT:    s_lshr_b64 s[4:5], s[6:7], 25
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s2
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v2i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    v_mov_b32_e32 v3, s6
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 23
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v3, 25
+; GFX9-NEXT:    s_mov_b32 s0, s7
+; GFX9-NEXT:    s_mov_b32 s1, s5
+; GFX9-NEXT:    s_mov_b32 s7, s4
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], 23
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], 25
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v2i32_imm:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
 ; R600-NEXT:    23(3.222986e-44), 0(0.000000e+00)
 ; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
 ; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_v2i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s7, 23
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s6, 25
+; GFX10-NEXT:    s_mov_b32 s0, s7
+; GFX10-NEXT:    s_mov_b32 s7, s4
+; GFX10-NEXT:    s_mov_b32 s1, s5
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[6:7], 25
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], 23
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v2i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s7, 23
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s6, 25
+; GFX11-NEXT:    s_mov_b32 s2, s7
+; GFX11-NEXT:    s_mov_b32 s7, s4
+; GFX11-NEXT:    s_mov_b32 s3, s5
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[6:7], 25
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], 23
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
   store <2 x i32> %0, <2 x i32> addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
 ; SI-LABEL: fshl_v4i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
-; SI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x15
-; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
+; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x15
+; SI-NEXT:    s_mov_b32 s15, 0xf000
+; SI-NEXT:    s_mov_b32 s14, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    s_not_b32 s11, s15
-; SI-NEXT:    v_alignbit_b32 v0, s7, v0, 1
-; SI-NEXT:    s_lshr_b32 s7, s7, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s11
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s10
-; SI-NEXT:    s_not_b32 s7, s14
-; SI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; SI-NEXT:    s_lshr_b32 s6, s6, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s7
-; SI-NEXT:    v_alignbit_b32 v2, s6, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    s_not_b32 s6, s13
-; SI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; SI-NEXT:    s_lshr_b32 s5, s5, 1
+; SI-NEXT:    s_mov_b32 s16, s11
+; SI-NEXT:    s_mov_b32 s17, s7
+; SI-NEXT:    s_lshr_b32 s18, s7, 1
+; SI-NEXT:    s_lshr_b64 s[16:17], s[16:17], 1
+; SI-NEXT:    s_mov_b32 s17, s18
+; SI-NEXT:    s_not_b32 s3, s3
+; SI-NEXT:    s_mov_b32 s11, s6
+; SI-NEXT:    s_lshr_b64 s[16:17], s[16:17], s3
+; SI-NEXT:    s_lshr_b32 s3, s6, 1
+; SI-NEXT:    s_lshr_b64 s[6:7], s[10:11], 1
+; SI-NEXT:    s_mov_b32 s7, s3
+; SI-NEXT:    s_not_b32 s2, s2
+; SI-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2
+; SI-NEXT:    s_mov_b32 s6, s9
+; SI-NEXT:    s_mov_b32 s7, s5
+; SI-NEXT:    s_lshr_b32 s3, s5, 1
+; SI-NEXT:    s_lshr_b64 s[6:7], s[6:7], 1
+; SI-NEXT:    s_mov_b32 s7, s3
+; SI-NEXT:    s_not_b32 s1, s1
+; SI-NEXT:    s_mov_b32 s9, s4
+; SI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s1
+; SI-NEXT:    s_lshr_b32 s1, s4, 1
+; SI-NEXT:    s_lshr_b64 s[4:5], s[8:9], 1
+; SI-NEXT:    s_mov_b32 s5, s1
+; SI-NEXT:    s_not_b32 s0, s0
+; SI-NEXT:    s_lshr_b64 s[0:1], s[4:5], s0
+; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    v_mov_b32_e32 v1, s6
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    s_not_b32 s5, s12
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; SI-NEXT:    s_lshr_b32 s4, s4, 1
-; SI-NEXT:    v_mov_b32_e32 v4, s5
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
-; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-NEXT:    v_mov_b32_e32 v2, s2
+; SI-NEXT:    v_mov_b32_e32 v3, s16
+; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v4i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
-; VI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
+; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    s_not_b32 s3, s15
-; VI-NEXT:    s_lshr_b32 s2, s7, 1
-; VI-NEXT:    v_alignbit_b32 v0, s7, v0, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v3, s2, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s10
-; VI-NEXT:    s_not_b32 s3, s14
-; VI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; VI-NEXT:    s_lshr_b32 s2, s6, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v2, s2, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s9
-; VI-NEXT:    s_not_b32 s3, s13
-; VI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; VI-NEXT:    s_lshr_b32 s2, s5, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v1, s2, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s8
-; VI-NEXT:    s_not_b32 s3, s12
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; VI-NEXT:    s_lshr_b32 s2, s4, 1
-; VI-NEXT:    v_mov_b32_e32 v4, s3
-; VI-NEXT:    v_alignbit_b32 v0, s2, v0, v4
-; VI-NEXT:    v_mov_b32_e32 v5, s1
-; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    s_mov_b32 s14, s11
+; VI-NEXT:    s_mov_b32 s15, s7
+; VI-NEXT:    s_lshr_b32 s16, s7, 1
+; VI-NEXT:    s_lshr_b64 s[14:15], s[14:15], 1
+; VI-NEXT:    s_mov_b32 s15, s16
+; VI-NEXT:    s_not_b32 s3, s3
+; VI-NEXT:    s_mov_b32 s11, s6
+; VI-NEXT:    s_lshr_b64 s[14:15], s[14:15], s3
+; VI-NEXT:    s_lshr_b32 s3, s6, 1
+; VI-NEXT:    s_lshr_b64 s[6:7], s[10:11], 1
+; VI-NEXT:    s_mov_b32 s7, s3
+; VI-NEXT:    s_not_b32 s2, s2
+; VI-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2
+; VI-NEXT:    s_mov_b32 s6, s9
+; VI-NEXT:    s_mov_b32 s7, s5
+; VI-NEXT:    s_lshr_b32 s3, s5, 1
+; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], 1
+; VI-NEXT:    s_mov_b32 s7, s3
+; VI-NEXT:    s_not_b32 s1, s1
+; VI-NEXT:    s_mov_b32 s9, s4
+; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s1
+; VI-NEXT:    s_lshr_b32 s1, s4, 1
+; VI-NEXT:    s_lshr_b64 s[4:5], s[8:9], 1
+; VI-NEXT:    s_mov_b32 s5, s1
+; VI-NEXT:    s_not_b32 s0, s0
+; VI-NEXT:    s_lshr_b64 s[0:1], s[4:5], s0
+; VI-NEXT:    v_mov_b32_e32 v4, s12
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s6
+; VI-NEXT:    v_mov_b32_e32 v2, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s14
+; VI-NEXT:    v_mov_b32_e32 v5, s13
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v4i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX9-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_not_b32 s1, s15
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
-; GFX9-NEXT:    s_lshr_b32 s0, s7, 1
-; GFX9-NEXT:    v_alignbit_b32 v0, s7, v0, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v3, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s10
+; GFX9-NEXT:    s_mov_b32 s0, s11
+; GFX9-NEXT:    s_mov_b32 s1, s7
+; GFX9-NEXT:    s_lshr_b32 s16, s7, 1
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
+; GFX9-NEXT:    s_mov_b32 s1, s16
+; GFX9-NEXT:    s_not_b32 s7, s15
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s7
+; GFX9-NEXT:    s_mov_b32 s11, s6
+; GFX9-NEXT:    s_lshr_b32 s1, s6, 1
+; GFX9-NEXT:    s_lshr_b64 s[6:7], s[10:11], 1
+; GFX9-NEXT:    s_mov_b32 s7, s1
 ; GFX9-NEXT:    s_not_b32 s1, s14
-; GFX9-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s6, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v2, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
+; GFX9-NEXT:    s_mov_b32 s10, s9
+; GFX9-NEXT:    s_mov_b32 s11, s5
+; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s1
+; GFX9-NEXT:    s_lshr_b32 s1, s5, 1
+; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], 1
+; GFX9-NEXT:    s_mov_b32 s11, s1
 ; GFX9-NEXT:    s_not_b32 s1, s13
-; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s5, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v1, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-NEXT:    s_mov_b32 s9, s4
+; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], s1
+; GFX9-NEXT:    s_lshr_b32 s1, s4, 1
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[8:9], 1
+; GFX9-NEXT:    s_mov_b32 s5, s1
 ; GFX9-NEXT:    s_not_b32 s1, s12
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s4, 1
-; GFX9-NEXT:    v_mov_b32_e32 v5, s1
-; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v5
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s1
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s10
+; GFX9-NEXT:    v_mov_b32_e32 v2, s6
+; GFX9-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v4i32:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END

 ; GFX10-LABEL: fshl_v4i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX10-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v0, s7, s11, 1
-; GFX10-NEXT:    v_alignbit_b32 v1, s6, s10, 1
-; GFX10-NEXT:    v_alignbit_b32 v5, s5, s9, 1
-; GFX10-NEXT:    v_alignbit_b32 v6, s4, s8, 1
-; GFX10-NEXT:    s_lshr_b32 s2, s7, 1
-; GFX10-NEXT:    s_not_b32 s3, s15
-; GFX10-NEXT:    s_lshr_b32 s6, s6, 1
-; GFX10-NEXT:    s_not_b32 s7, s14
-; GFX10-NEXT:    s_lshr_b32 s5, s5, 1
-; GFX10-NEXT:    s_not_b32 s9, s13
-; GFX10-NEXT:    s_lshr_b32 s4, s4, 1
-; GFX10-NEXT:    s_not_b32 s8, s12
-; GFX10-NEXT:    v_alignbit_b32 v3, s2, v0, s3
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, v1, s7
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, v5, s9
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, v6, s8
+; GFX10-NEXT:    s_mov_b32 s2, s11
+; GFX10-NEXT:    s_mov_b32 s3, s7
+; GFX10-NEXT:    s_lshr_b32 s16, s7, 1
+; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
+; GFX10-NEXT:    s_not_b32 s15, s15
+; GFX10-NEXT:    s_lshr_b32 s17, s6, 1
+; GFX10-NEXT:    s_mov_b32 s11, s6
+; GFX10-NEXT:    s_mov_b32 s6, s9
+; GFX10-NEXT:    s_mov_b32 s7, s5
+; GFX10-NEXT:    s_mov_b32 s9, s4
+; GFX10-NEXT:    s_mov_b32 s3, s16
+; GFX10-NEXT:    s_lshr_b32 s18, s5, 1
+; GFX10-NEXT:    s_lshr_b32 s19, s4, 1
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[10:11], 1
+; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], 1
+; GFX10-NEXT:    s_lshr_b64 s[8:9], s[8:9], 1
+; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s15
+; GFX10-NEXT:    s_not_b32 s14, s14
+; GFX10-NEXT:    s_not_b32 s12, s12
+; GFX10-NEXT:    s_mov_b32 s5, s17
+; GFX10-NEXT:    s_mov_b32 s7, s18
+; GFX10-NEXT:    s_mov_b32 s9, s19
+; GFX10-NEXT:    s_not_b32 s3, s13
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[4:5], s14
+; GFX10-NEXT:    s_lshr_b64 s[8:9], s[8:9], s12
+; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s3
+; GFX10-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10-NEXT:    v_mov_b32_e32 v1, s6
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v4i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
 ; GFX11-NEXT:    s_load_b128 s[12:15], s[0:1], 0x54
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, s7, s11, 1
-; GFX11-NEXT:    v_alignbit_b32 v1, s6, s10, 1
-; GFX11-NEXT:    v_alignbit_b32 v5, s5, s9, 1
-; GFX11-NEXT:    v_alignbit_b32 v6, s4, s8, 1
-; GFX11-NEXT:    s_lshr_b32 s2, s7, 1
-; GFX11-NEXT:    s_not_b32 s3, s15
-; GFX11-NEXT:    s_lshr_b32 s6, s6, 1
-; GFX11-NEXT:    s_not_b32 s7, s14
-; GFX11-NEXT:    s_lshr_b32 s5, s5, 1
-; GFX11-NEXT:    s_not_b32 s9, s13
-; GFX11-NEXT:    s_lshr_b32 s4, s4, 1
-; GFX11-NEXT:    s_not_b32 s8, s12
-; GFX11-NEXT:    v_alignbit_b32 v3, s2, v0, s3
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, v1, s7
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, v5, s9
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, v6, s8
+; GFX11-NEXT:    s_mov_b32 s2, s11
+; GFX11-NEXT:    s_mov_b32 s3, s7
+; GFX11-NEXT:    s_lshr_b32 s16, s7, 1
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT:    s_not_b32 s15, s15
+; GFX11-NEXT:    s_lshr_b32 s17, s6, 1
+; GFX11-NEXT:    s_mov_b32 s11, s6
+; GFX11-NEXT:    s_mov_b32 s6, s9
+; GFX11-NEXT:    s_mov_b32 s7, s5
+; GFX11-NEXT:    s_mov_b32 s9, s4
+; GFX11-NEXT:    s_mov_b32 s3, s16
+; GFX11-NEXT:    s_lshr_b32 s18, s5, 1
+; GFX11-NEXT:    s_lshr_b32 s19, s4, 1
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[10:11], 1
+; GFX11-NEXT:    s_lshr_b64 s[6:7], s[6:7], 1
+; GFX11-NEXT:    s_lshr_b64 s[8:9], s[8:9], 1
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], s15
+; GFX11-NEXT:    s_not_b32 s14, s14
+; GFX11-NEXT:    s_not_b32 s12, s12
+; GFX11-NEXT:    s_mov_b32 s5, s17
+; GFX11-NEXT:    s_mov_b32 s7, s18
+; GFX11-NEXT:    s_mov_b32 s9, s19
+; GFX11-NEXT:    s_not_b32 s3, s13
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[4:5], s14
+; GFX11-NEXT:    s_lshr_b64 s[8:9], s[8:9], s12
+; GFX11-NEXT:    s_lshr_b64 s[6:7], s[6:7], s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s6
+; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
   store <4 x i32> %0, <4 x i32> addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
 ; SI-LABEL: fshl_v4i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
+; SI-NEXT:    s_mov_b32 s12, s11
+; SI-NEXT:    s_mov_b32 s11, s6
+; SI-NEXT:    s_mov_b32 s13, s7
+; SI-NEXT:    s_lshr_b64 s[6:7], s[10:11], 23
+; SI-NEXT:    s_mov_b32 s10, s9
+; SI-NEXT:    s_mov_b32 s11, s5
+; SI-NEXT:    s_mov_b32 s9, s4
+; SI-NEXT:    s_lshr_b64 s[12:13], s[12:13], 31
+; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], 25
+; SI-NEXT:    s_lshr_b64 s[4:5], s[8:9], 31
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, 31
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    v_alignbit_b32 v2, s6, v1, 23
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 25
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 31
+; SI-NEXT:    v_mov_b32_e32 v2, s6
+; SI-NEXT:    v_mov_b32_e32 v3, s12
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v4i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    v_mov_b32_e32 v1, s10
-; VI-NEXT:    v_mov_b32_e32 v4, s9
-; VI-NEXT:    v_alignbit_b32 v3, s7, v0, 31
-; VI-NEXT:    v_alignbit_b32 v2, s6, v1, 23
-; VI-NEXT:    v_alignbit_b32 v1, s5, v4, 25
-; VI-NEXT:    v_mov_b32_e32 v0, s8
+; VI-NEXT:    s_mov_b32 s2, s11
+; VI-NEXT:    s_mov_b32 s11, s6
+; VI-NEXT:    s_mov_b32 s3, s7
+; VI-NEXT:    s_lshr_b64 s[6:7], s[10:11], 23
+; VI-NEXT:    s_mov_b32 s10, s9
+; VI-NEXT:    s_mov_b32 s11, s5
+; VI-NEXT:    s_mov_b32 s9, s4
+; VI-NEXT:    s_lshr_b64 s[2:3], s[2:3], 31
+; VI-NEXT:    s_lshr_b64 s[10:11], s[10:11], 25
+; VI-NEXT:    s_lshr_b64 s[4:5], s[8:9], 31
 ; VI-NEXT:    v_mov_b32_e32 v5, s1
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 31
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s10
+; VI-NEXT:    v_mov_b32_e32 v2, s6
+; VI-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v4i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
+; GFX9-NEXT:    s_mov_b32 s2, s11
+; GFX9-NEXT:    s_mov_b32 s11, s6
+; GFX9-NEXT:    s_mov_b32 s3, s7
+; GFX9-NEXT:    s_lshr_b64 s[6:7], s[10:11], 23
+; GFX9-NEXT:    s_mov_b32 s10, s9
+; GFX9-NEXT:    s_mov_b32 s11, s5
+; GFX9-NEXT:    s_mov_b32 s9, s4
+; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], 31
+; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], 25
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[8:9], 31
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s10
-; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, 31
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
-; GFX9-NEXT:    v_alignbit_b32 v2, s6, v1, 23
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 25
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 31
+; GFX9-NEXT:    v_mov_b32_e32 v2, s6
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v4i32_imm:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END

 ;
 ; GFX10-LABEL: fshl_v4i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v3, s7, s11, 31
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, s10, 23
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s9, 25
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s8, 31
+; GFX10-NEXT:    s_mov_b32 s0, s11
+; GFX10-NEXT:    s_mov_b32 s1, s7
+; GFX10-NEXT:    s_mov_b32 s11, s6
+; GFX10-NEXT:    s_mov_b32 s6, s9
+; GFX10-NEXT:    s_mov_b32 s7, s5
+; GFX10-NEXT:    s_mov_b32 s9, s4
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], 31
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[10:11], 23
+; GFX10-NEXT:    s_lshr_b64 s[8:9], s[8:9], 31
+; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], 25
+; GFX10-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10-NEXT:    v_mov_b32_e32 v1, s6
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v4i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v3, s7, s11, 31
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, s10, 23
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s9, 25
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s8, 31
+; GFX11-NEXT:    s_mov_b32 s2, s11
+; GFX11-NEXT:    s_mov_b32 s3, s7
+; GFX11-NEXT:    s_mov_b32 s11, s6
+; GFX11-NEXT:    s_mov_b32 s6, s9
+; GFX11-NEXT:    s_mov_b32 s7, s5
+; GFX11-NEXT:    s_mov_b32 s9, s4
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], 31
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[10:11], 23
+; GFX11-NEXT:    s_lshr_b64 s[8:9], s[8:9], 31
+; GFX11-NEXT:    s_lshr_b64 s[6:7], s[6:7], 25
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s6
+; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
   store <4 x i32> %0, <4 x i32> addrspace(1)* %in
   ret void
 }

llvm/test/CodeGen/AMDGPU/fshr.ll

 define amdgpu_kernel void @fshr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %z) {
 ; SI-LABEL: fshr_i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; SI-NEXT:    s_load_dword s8, s[0:1], 0xd
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v1, s8
 ; SI-NEXT:    s_mov_b32 s0, s4
 ; SI-NEXT:    s_mov_b32 s1, s5
-; SI-NEXT:    v_alignbit_b32 v0, s6, v0, v1
+; SI-NEXT:    s_mov_b32 s4, s7
+; SI-NEXT:    s_mov_b32 s5, s6
+; SI-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; VI-NEXT:    s_load_dword s0, s[0:1], 0x34
+; VI-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v1, s0
-; VI-NEXT:    v_alignbit_b32 v2, s6, v0, v1
+; VI-NEXT:    s_mov_b32 s0, s7
+; VI-NEXT:    s_mov_b32 s1, s6
+; VI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s7
-; GFX9-NEXT:    v_mov_b32_e32 v2, s2
-; GFX9-NEXT:    v_alignbit_b32 v1, s6, v1, v2
+; GFX9-NEXT:    s_mov_b32 s0, s7
+; GFX9-NEXT:    s_mov_b32 s1, s6
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_i32:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 2, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,
 ;
 ; GFX10-LABEL: fshr_i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
+; GFX10-NEXT:    s_load_dword s2, s[0:1], 0x34
+; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, s2
-; GFX10-NEXT:    v_alignbit_b32 v0, s6, s7, v0
-; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]
+; GFX10-NEXT:    s_mov_b32 s0, s7
+; GFX10-NEXT:    s_mov_b32 s1, s6
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s4, s[0:1], 0x34
-; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX11-NEXT:    s_load_b32 s2, s[0:1], 0x34
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s2, s3, v0
-; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT:    s_mov_b32 s0, s7
+; GFX11-NEXT:    s_mov_b32 s1, s6
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT:    global_store_b32 v0, v1, s[4:5]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
   store i32 %0, i32 addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_i32_imm(i32 addrspace(1)* %in, i32 %x, i32 %y) {
 ; SI-LABEL: fshr_i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s3
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
-; SI-NEXT:    v_alignbit_b32 v0, s2, v0, 7
+; SI-NEXT:    s_mov_b32 s0, s3
+; SI-NEXT:    s_mov_b32 s1, s2
+; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], 7
+; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_alignbit_b32 v2, s2, v0, 7
+; VI-NEXT:    s_mov_b32 s4, s3
+; VI-NEXT:    s_mov_b32 s5, s2
+; VI-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_alignbit_b32 v1, s2, v1, 7
+; GFX9-NEXT:    s_mov_b32 s4, s3
+; GFX9-NEXT:    s_mov_b32 s5, s2
+; GFX9-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_i32_imm:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
 ; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s2, s3, 7
+; GFX10-NEXT:    s_mov_b32 s4, s3
+; GFX10-NEXT:    s_mov_b32 s5, s2
+; GFX10-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7
+; GFX10-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s2, s3, 7
+; GFX11-NEXT:    s_mov_b32 s4, s3
+; GFX11-NEXT:    s_mov_b32 s5, s2
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[4:5], 7
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
 ; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)
   store i32 %0, i32 addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; SI-LABEL: fshr_v2i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
-; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xf
-; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xf
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v1, s9
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s6
-; SI-NEXT:    v_mov_b32_e32 v2, s8
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v2
-; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT:    s_mov_b32 s2, s7
+; SI-NEXT:    s_mov_b32 s3, s5
+; SI-NEXT:    s_mov_b32 s7, s4
+; SI-NEXT:    s_lshr_b64 s[2:3], s[2:3], s1
+; SI-NEXT:    s_lshr_b64 s[0:1], s[6:7], s0
+; SI-NEXT:    v_mov_b32_e32 v0, s0
+; SI-NEXT:    v_mov_b32_e32 v1, s2
+; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v2i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_mov_b32_e32 v2, s6
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s2
-; VI-NEXT:    v_alignbit_b32 v0, s4, v2, v0
+; VI-NEXT:    s_mov_b32 s8, s7
+; VI-NEXT:    s_mov_b32 s9, s5
+; VI-NEXT:    s_mov_b32 s7, s4
+; VI-NEXT:    s_lshr_b64 s[4:5], s[8:9], s3
+; VI-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s4
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v2i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s6
-; GFX9-NEXT:    v_mov_b32_e32 v3, s2
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v3
+; GFX9-NEXT:    s_mov_b32 s0, s7
+; GFX9-NEXT:    s_mov_b32 s1, s5
+; GFX9-NEXT:    s_mov_b32 s7, s4
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s3
+; GFX9-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2
+; GFX9-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v2i32:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     MOV * T0.W, KC0[4].X,
 ; R600-NEXT:     BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].Z, PV.W,
 ; R600-NEXT:     MOV * T0.W, KC0[3].W,
 ; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, PV.W,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_v2i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x2
-; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX10-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
-; GFX10-NEXT:    v_mov_b32_e32 v3, 0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, s3
-; GFX10-NEXT:    v_mov_b32_e32 v2, s2
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s7, v0
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s6, v2
-; GFX10-NEXT:    global_store_dwordx2 v3, v[0:1], s[8:9]
+; GFX10-NEXT:    s_mov_b32 s0, s7
+; GFX10-NEXT:    s_mov_b32 s7, s4
+; GFX10-NEXT:    s_mov_b32 s1, s5
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[6:7], s2
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s3
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v2i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x3c
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
+; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x3c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s3
-; GFX11-NEXT:    v_mov_b32_e32 v2, s2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s7, v0
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s6, v2
-; GFX11-NEXT:    global_store_b64 v3, v[0:1], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s8, s7
+; GFX11-NEXT:    s_mov_b32 s7, s4
+; GFX11-NEXT:    s_mov_b32 s9, s5
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[6:7], s2
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[8:9], s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT:    v_mov_b32_e32 v0, s4
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
   store <2 x i32> %0, <2 x i32> addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
 ; SI-LABEL: fshr_v2i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v2, s6
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 9
-; SI-NEXT:    v_alignbit_b32 v0, s4, v2, 7
+; SI-NEXT:    s_mov_b32 s8, s7
+; SI-NEXT:    s_mov_b32 s9, s5
+; SI-NEXT:    s_mov_b32 s7, s4
+; SI-NEXT:    s_lshr_b64 s[8:9], s[8:9], 9
+; SI-NEXT:    s_lshr_b64 s[4:5], s[6:7], 7
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s8
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v2i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v2, s6
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 9
-; VI-NEXT:    v_alignbit_b32 v0, s4, v2, 7
+; VI-NEXT:    s_mov_b32 s2, s7
+; VI-NEXT:    s_mov_b32 s3, s5
+; VI-NEXT:    s_mov_b32 s7, s4
+; VI-NEXT:    s_lshr_b64 s[2:3], s[2:3], 9
+; VI-NEXT:    s_lshr_b64 s[4:5], s[6:7], 7
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s2
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v2i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    v_mov_b32_e32 v3, s6
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 9
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v3, 7
+; GFX9-NEXT:    s_mov_b32 s0, s7
+; GFX9-NEXT:    s_mov_b32 s1, s5
+; GFX9-NEXT:    s_mov_b32 s7, s4
+; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], 9
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], 7
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v2i32_imm:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
 ; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)
 ; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
 ; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_v2i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s7, 9
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s6, 7
+; GFX10-NEXT:    s_mov_b32 s0, s7
+; GFX10-NEXT:    s_mov_b32 s7, s4
+; GFX10-NEXT:    s_mov_b32 s1, s5
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[6:7], 7
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], 9
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v2i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s7, 9
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s6, 7
+; GFX11-NEXT:    s_mov_b32 s2, s7
+; GFX11-NEXT:    s_mov_b32 s7, s4
+; GFX11-NEXT:    s_mov_b32 s3, s5
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[6:7], 7
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], 9
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
   store <2 x i32> %0, <2 x i32> addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
 ; SI-LABEL: fshr_v4i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; SI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x15
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    v_mov_b32_e32 v1, s15
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s10
-; SI-NEXT:    v_mov_b32_e32 v1, s14
-; SI-NEXT:    v_alignbit_b32 v2, s6, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    v_mov_b32_e32 v1, s13
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    v_mov_b32_e32 v4, s12
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
+; SI-NEXT:    s_mov_b32 s16, s11
+; SI-NEXT:    s_mov_b32 s11, s6
+; SI-NEXT:    s_mov_b32 s17, s7
+; SI-NEXT:    s_lshr_b64 s[6:7], s[10:11], s14
+; SI-NEXT:    s_mov_b32 s10, s9
+; SI-NEXT:    s_mov_b32 s11, s5
+; SI-NEXT:    s_mov_b32 s9, s4
+; SI-NEXT:    s_lshr_b64 s[16:17], s[16:17], s15
+; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], s13
+; SI-NEXT:    s_lshr_b64 s[4:5], s[8:9], s12
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s10
+; SI-NEXT:    v_mov_b32_e32 v2, s6
+; SI-NEXT:    v_mov_b32_e32 v3, s16
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v4i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    v_mov_b32_e32 v1, s15
-; VI-NEXT:    v_mov_b32_e32 v2, s10
-; VI-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s14
-; VI-NEXT:    v_alignbit_b32 v2, s6, v2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s9
-; VI-NEXT:    v_mov_b32_e32 v1, s13
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s8
-; VI-NEXT:    v_mov_b32_e32 v4, s12
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
+; VI-NEXT:    s_mov_b32 s2, s11
+; VI-NEXT:    s_mov_b32 s11, s6
+; VI-NEXT:    s_mov_b32 s3, s7
+; VI-NEXT:    s_lshr_b64 s[6:7], s[10:11], s14
+; VI-NEXT:    s_mov_b32 s10, s9
+; VI-NEXT:    s_mov_b32 s11, s5
+; VI-NEXT:    s_mov_b32 s9, s4
+; VI-NEXT:    s_lshr_b64 s[2:3], s[2:3], s15
+; VI-NEXT:    s_lshr_b64 s[10:11], s[10:11], s13
+; VI-NEXT:    s_lshr_b64 s[4:5], s[8:9], s12
 ; VI-NEXT:    v_mov_b32_e32 v5, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s10
+; VI-NEXT:    v_mov_b32_e32 v2, s6
+; VI-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v4i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
-; GFX9-NEXT:    v_mov_b32_e32 v1, s15
-; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s10
-; GFX9-NEXT:    v_mov_b32_e32 v1, s14
-; GFX9-NEXT:    v_alignbit_b32 v2, s6, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
-; GFX9-NEXT:    v_mov_b32_e32 v1, s13
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
-; GFX9-NEXT:    v_mov_b32_e32 v5, s12
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v5
+; GFX9-NEXT:    s_mov_b32 s2, s11
+; GFX9-NEXT:    s_mov_b32 s11, s6
+; GFX9-NEXT:    s_mov_b32 s3, s7
+; GFX9-NEXT:    s_lshr_b64 s[6:7], s[10:11], s14
+; GFX9-NEXT:    s_mov_b32 s10, s9
+; GFX9-NEXT:    s_mov_b32 s11, s5
+; GFX9-NEXT:    s_mov_b32 s9, s4
+; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], s15
+; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], s13
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[8:9], s12
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s10
+; GFX9-NEXT:    v_mov_b32_e32 v2, s6
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v4i32:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     MOV * T0.W, KC0[6].X,
 ; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W,
 ; R600-NEXT:     MOV * T1.W, KC0[5].W,
 ; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, PV.W,
 ; R600-NEXT:     MOV * T1.W, KC0[5].Z,
 ; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W,
 ; R600-NEXT:     MOV * T1.W, KC0[5].Y,
 ; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_v4i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x2
-; GFX10-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
+; GFX10-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX10-NEXT:    v_mov_b32_e32 v6, 0
+; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, s15
-; GFX10-NEXT:    v_mov_b32_e32 v1, s14
-; GFX10-NEXT:    v_mov_b32_e32 v4, s13
-; GFX10-NEXT:    v_mov_b32_e32 v5, s12
-; GFX10-NEXT:    v_alignbit_b32 v3, s7, s11, v0
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, s10, v1
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s9, v4
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s8, v5
-; GFX10-NEXT:    global_store_dwordx4 v6, v[0:3], s[2:3]
+; GFX10-NEXT:    s_mov_b32 s0, s11
+; GFX10-NEXT:    s_mov_b32 s1, s7
+; GFX10-NEXT:    s_mov_b32 s11, s6
+; GFX10-NEXT:    s_mov_b32 s6, s9
+; GFX10-NEXT:    s_mov_b32 s7, s5
+; GFX10-NEXT:    s_mov_b32 s9, s4
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s15
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[10:11], s14
+; GFX10-NEXT:    s_lshr_b64 s[8:9], s[8:9], s12
+; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s13
+; GFX10-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10-NEXT:    v_mov_b32_e32 v1, s6
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_mov_b32_e32 v3, s0
+; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v4i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    s_load_b128 s[12:15], s[0:1], 0x54
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
+; GFX11-NEXT:    s_load_b128 s[12:15], s[0:1], 0x54
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v0, s15 :: v_dual_mov_b32 v1, s14
-; GFX11-NEXT:    v_dual_mov_b32 v4, s13 :: v_dual_mov_b32 v5, s12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_alignbit_b32 v3, s7, s11, v0
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, s10, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s9, v4
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s8, v5
-; GFX11-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s2, s11
+; GFX11-NEXT:    s_mov_b32 s3, s7
+; GFX11-NEXT:    s_mov_b32 s11, s6
+; GFX11-NEXT:    s_mov_b32 s6, s9
+; GFX11-NEXT:    s_mov_b32 s7, s5
+; GFX11-NEXT:    s_mov_b32 s9, s4
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], s15
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[10:11], s14
+; GFX11-NEXT:    s_lshr_b64 s[8:9], s[8:9], s12
+; GFX11-NEXT:    s_lshr_b64 s[6:7], s[6:7], s13
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s6
+; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s4
+; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
   store <4 x i32> %0, <4 x i32> addrspace(1)* %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
 ; SI-LABEL: fshr_v4i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
+; SI-NEXT:    s_mov_b32 s12, s11
+; SI-NEXT:    s_mov_b32 s11, s6
+; SI-NEXT:    s_mov_b32 s13, s7
+; SI-NEXT:    s_lshr_b64 s[6:7], s[10:11], 9
+; SI-NEXT:    s_mov_b32 s10, s9
+; SI-NEXT:    s_mov_b32 s11, s5
+; SI-NEXT:    s_mov_b32 s9, s4
+; SI-NEXT:    s_lshr_b64 s[12:13], s[12:13], 1
+; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], 7
+; SI-NEXT:    s_lshr_b64 s[4:5], s[8:9], 1
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, 1
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    v_alignbit_b32 v2, s6, v1, 9
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 7
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
+; SI-NEXT:    v_mov_b32_e32 v2, s6
+; SI-NEXT:    v_mov_b32_e32 v3, s12
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v4i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    v_mov_b32_e32 v1, s10
-; VI-NEXT:    v_mov_b32_e32 v4, s9
-; VI-NEXT:    v_alignbit_b32 v3, s7, v0, 1
-; VI-NEXT:    v_alignbit_b32 v2, s6, v1, 9
-; VI-NEXT:    v_alignbit_b32 v1, s5, v4, 7
-; VI-NEXT:    v_mov_b32_e32 v0, s8
+; VI-NEXT:    s_mov_b32 s2, s11
+; VI-NEXT:    s_mov_b32 s11, s6
+; VI-NEXT:    s_mov_b32 s3, s7
+; VI-NEXT:    s_lshr_b64 s[6:7], s[10:11], 9
+; VI-NEXT:    s_mov_b32 s10, s9
+; VI-NEXT:    s_mov_b32 s11, s5
+; VI-NEXT:    s_mov_b32 s9, s4
+; VI-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
+; VI-NEXT:    s_lshr_b64 s[10:11], s[10:11], 7
+; VI-NEXT:    s_lshr_b64 s[4:5], s[8:9], 1
 ; VI-NEXT:    v_mov_b32_e32 v5, s1
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s10
+; VI-NEXT:    v_mov_b32_e32 v2, s6
+; VI-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v4i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
+; GFX9-NEXT:    s_mov_b32 s2, s11
+; GFX9-NEXT:    s_mov_b32 s11, s6
+; GFX9-NEXT:    s_mov_b32 s3, s7
+; GFX9-NEXT:    s_lshr_b64 s[6:7], s[10:11], 9
+; GFX9-NEXT:    s_mov_b32 s10, s9
+; GFX9-NEXT:    s_mov_b32 s11, s5
+; GFX9-NEXT:    s_mov_b32 s9, s4
+; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
+; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], 7
+; GFX9-NEXT:    s_lshr_b64 s[4:5], s[8:9], 1
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s10
-; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, 1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
-; GFX9-NEXT:    v_alignbit_b32 v2, s6, v1, 9
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 7
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s6
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v4i32_imm:
 ; R600:       ; %bb.0: ; %entry
 ; R600-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END

 ;
 ; GFX10-LABEL: fshr_v4i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v3, s7, s11, 1
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, s10, 9
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s9, 7
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s8, 1
+; GFX10-NEXT:    s_mov_b32 s0, s11
+; GFX10-NEXT:    s_mov_b32 s1, s7
+; GFX10-NEXT:    s_mov_b32 s11, s6
+; GFX10-NEXT:    s_mov_b32 s6, s9
+; GFX10-NEXT:    s_mov_b32 s7, s5
+; GFX10-NEXT:    s_mov_b32 s9, s4
+; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
+; GFX10-NEXT:    s_lshr_b64 s[4:5], s[10:11], 9
+; GFX10-NEXT:    s_lshr_b64 s[8:9], s[8:9], 1
+; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], 7
+; GFX10-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10-NEXT:    v_mov_b32_e32 v1, s6
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v4i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v3, s7, s11, 1
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, s10, 9
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s9, 7
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s8, 1
+; GFX11-NEXT:    s_mov_b32 s2, s11
+; GFX11-NEXT:    s_mov_b32 s3, s7
+; GFX11-NEXT:    s_mov_b32 s11, s6
+; GFX11-NEXT:    s_mov_b32 s6, s9
+; GFX11-NEXT:    s_mov_b32 s7, s5
+; GFX11-NEXT:    s_mov_b32 s9, s4
+; GFX11-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
+; GFX11-NEXT:    s_lshr_b64 s[4:5], s[10:11], 9
+; GFX11-NEXT:    s_lshr_b64 s[8:9], s[8:9], 1
+; GFX11-NEXT:    s_lshr_b64 s[6:7], s[6:7], 7
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s6
+; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
   store <4 x i32> %0, <4 x i32> addrspace(1)* %in
   ret void
 }

llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

 ;
 ; VI-LABEL: s_insertelement_v2i16_0_reghi:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_lshr_b32 s0, s2, 16
-; VI-NEXT:    v_alignbit_b32 v2, s0, v2, 16
+; VI-NEXT:    s_lshr_b32 s5, s2, 16
+; VI-NEXT:    s_lshr_b64 s[0:1], s[4:5], 16
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: s_insertelement_v2i16_0_reghi:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)

 ; GFX9-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_lshr_b32 s0, s4, 16
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    s_lshr_b32 s3, s4, 16
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_lshr_b32 s1, s2, 16
-; VI-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; VI-NEXT:    s_lshr_b32 s5, s2, 16
+; VI-NEXT:    s_lshr_b64 s[0:1], s[4:5], 16
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    ;;#ASMSTART
-; VI-NEXT:    ; use s0
+; VI-NEXT:    ; use s3
 ; VI-NEXT:    ;;#ASMEND
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)

 ; GFX9-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_lshr_b32 s0, s4, 16
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    s_lshr_b32 s3, s4, 16
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_lshr_b32 s1, s2, 16
-; VI-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; VI-NEXT:    s_lshr_b32 s5, s2, 16
+; VI-NEXT:    s_lshr_b64 s[0:1], s[4:5], 16
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    ;;#ASMSTART
-; VI-NEXT:    ; use s0
+; VI-NEXT:    ; use s3
 ; VI-NEXT:    ;;#ASMEND
 ; VI-NEXT:    ;;#ASMSTART
-; VI-NEXT:    ; use s1
+; VI-NEXT:    ; use s5
 ; VI-NEXT:    ;;#ASMEND
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_mov_b32_e32 v2, s4
 ; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    s_lshr_b32 s0, s4, 16
+; CI-NEXT:    v_mov_b32_e32 v1, s1
+; CI-NEXT:    s_lshr_b32 s3, s4, 16
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_lshr_b32 s1, s2, 16
-; CI-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; CI-NEXT:    s_lshr_b32 s5, s2, 16
+; CI-NEXT:    s_lshr_b64 s[0:1], s[4:5], 16
+; CI-NEXT:    v_mov_b32_e32 v2, s0
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    ;;#ASMSTART
-; CI-NEXT:    ; use s0
+; CI-NEXT:    ; use s3
 ; CI-NEXT:    ;;#ASMEND
 ; CI-NEXT:    ;;#ASMSTART
-; CI-NEXT:    ; use s1
+; CI-NEXT:    ; use s5
 ; CI-NEXT:    ;;#ASMEND
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x0
 ; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x10

llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll

 ; SI-NEXT:    s_mov_b32 s10, s6
 ; SI-NEXT:    s_mov_b32 s11, s7
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s8, s2
 ; SI-NEXT:    s_mov_b32 s9, s3
 ; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
 ; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 16
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
 ; SI-NEXT:    v_mov_b32_e32 v1, v0
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: scalar_to_vector_v2i32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s7, 0xf000
 ; VI-NEXT:    s_mov_b32 s6, -1
 ; VI-NEXT:    s_mov_b32 s10, s6
 ; VI-NEXT:    s_mov_b32 s11, s7
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_mov_b32 s8, s2
 ; VI-NEXT:    s_mov_b32 s9, s3
 ; VI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; VI-NEXT:    s_mov_b32 s4, s0
 ; VI-NEXT:    s_mov_b32 s5, s1
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]
 ; VI-NEXT:    v_mov_b32_e32 v1, v0
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
   %tmp1 = load i32, i32 addrspace(1)* %in, align 4
   %bc = bitcast i32 %tmp1 to <2 x i16>
   %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
   ret void
 }
 
 define amdgpu_kernel void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
 ; SI-LABEL: scalar_to_vector_v2f32:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_mov_b32 s10, s6
 ; SI-NEXT:    s_mov_b32 s11, s7
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s8, s2
 ; SI-NEXT:    s_mov_b32 s9, s3
 ; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
 ; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 16
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
 ; SI-NEXT:    v_mov_b32_e32 v1, v0
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: scalar_to_vector_v2f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s7, 0xf000
 ; VI-NEXT:    s_mov_b32 s6, -1
 ; VI-NEXT:    s_mov_b32 s10, s6
 ; VI-NEXT:    s_mov_b32 s11, s7
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_mov_b32 s8, s2
 ; VI-NEXT:    s_mov_b32 s9, s3
 ; VI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; VI-NEXT:    s_mov_b32 s4, s0
 ; VI-NEXT:    s_mov_b32 s5, s1
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]
 ; VI-NEXT:    v_mov_b32_e32 v1, v0
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
   %tmp1 = load float, float addrspace(1)* %in, align 4
   %bc = bitcast float %tmp1 to <2 x i16>
   %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
   ret void