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Differential D137596

[CodeGen][Test] simplify callbr-asm-outputs.ll with nounwind NFC
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Authored by nickdesaulniers on Nov 7 2022, 3:59 PM.

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void
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rG6a8d894ce053: [CodeGen][Test] simplify callbr-asm-outputs.ll with nounwind NFC
Summary

The CFI directives add noise to the test. Remove them via nounwind fn
attrs. Also remove clobbers.

Diff Detail

Unit TestsFailed

TimeTest
60,050 msx64 debian > MLIR.Examples/standalone::test.toy

Event Timeline

nickdesaulniers created this revision.Nov 7 2022, 3:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 7 2022, 3:59 PM
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nickdesaulniers requested review of this revision.Nov 7 2022, 3:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 7 2022, 3:59 PM
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void accepted this revision.Nov 7 2022, 4:02 PM
This revision is now accepted and ready to land.Nov 7 2022, 4:02 PM
Harbormaster completed remote builds in B196590: Diff 473818.Nov 7 2022, 4:51 PM
This revision was landed with ongoing or failed builds.Nov 10 2022, 2:26 PM
Closed by commit rG6a8d894ce053: [CodeGen][Test] simplify callbr-asm-outputs.ll with nounwind NFC (authored by nickdesaulniers). · Explain Why
This revision was automatically updated to reflect the committed changes.
nickdesaulniers added a commit: rG6a8d894ce053: [CodeGen][Test] simplify callbr-asm-outputs.ll with nounwind NFC.

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
30 lines

Diff 473818

llvm/test/CodeGen/X86/callbr-asm-outputs.ll

Show All 15 Lines
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_2: # Block address taken ; CHECK-NEXT: .LBB0_2: # Block address taken
; CHECK-NEXT: # %abnormal ; CHECK-NEXT: # %abnormal
; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%add = add nsw i32 %x, 4 %add = add nsw i32 %x, 4
%ret = callbr i32 asm "xorl $1, $0; jmp ${2:l}", "=r,r,!i,~{dirflag},~{fpsr},~{flags}"(i32 %add) %ret = callbr i32 asm "xorl $1, $0; jmp ${2:l}", "=r,r,!i"(i32 %add)
to label %normal [label %abnormal] to label %normal [label %abnormal]
normal: normal:
ret i32 %ret ret i32 %ret
abnormal: abnormal:
ret i32 1 ret i32 1
} }
define i32 @test2(i32 %out1, i32 %out2) { define i32 @test2(i32 %out1, i32 %out2) nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: .cfi_offset %esi, -12
; CHECK-NEXT: .cfi_offset %edi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl $-1, %eax ; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cmpl %edi, %esi ; CHECK-NEXT: cmpl %edi, %esi
; CHECK-NEXT: jge .LBB1_2 ; CHECK-NEXT: jge .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: testl %esi, %esi ; CHECK-NEXT: testl %esi, %esi
Show All 9 Lines
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB1_3: ; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: addl %edi, %eax ; CHECK-NEXT: addl %edi, %eax
; CHECK-NEXT: .LBB1_5: # Block address taken ; CHECK-NEXT: .LBB1_5: # Block address taken
; CHECK-NEXT: # %return ; CHECK-NEXT: # %return
; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_4: # Block address taken ; CHECK-NEXT: .LBB1_4: # Block address taken
; CHECK-NEXT: # %label_true ; CHECK-NEXT: # %label_true
; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movl $-2, %eax ; CHECK-NEXT: movl $-2, %eax
; CHECK-NEXT: jmp .LBB1_5 ; CHECK-NEXT: jmp .LBB1_5
entry: entry:
%cmp = icmp slt i32 %out1, %out2 %cmp = icmp slt i32 %out1, %out2
br i1 %cmp, label %if.then, label %if.else br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
%0 = callbr { i32, i32 } asm sideeffect "testl $0, $0; testl $1, $2; jne ${3:l}", "={si},={di},r,!i,!i,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %out1, i32 %out1, i32 %out2) %0 = callbr { i32, i32 } asm sideeffect "testl $0, $0; testl $1, $2; jne ${3:l}", "={si},={di},r,!i,!i,0,1"(i32 %out1, i32 %out1, i32 %out2)
to label %if.end [label %label_true, label %return] to label %if.end [label %label_true, label %return]
if.else: ; preds = %entry if.else: ; preds = %entry
%1 = callbr { i32, i32 } asm sideeffect "testl $0, $1; testl $2, $3; jne ${5:l}", "={si},={di},r,r,!i,!i,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %out1, i32 %out2, i32 %out1, i32 %out2) %1 = callbr { i32, i32 } asm sideeffect "testl $0, $1; testl $2, $3; jne ${5:l}", "={si},={di},r,r,!i,!i,0,1"(i32 %out1, i32 %out2, i32 %out1, i32 %out2)
to label %if.end [label %label_true, label %return] to label %if.end [label %label_true, label %return]
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
%.sink11 = phi { i32, i32 } [ %0, %if.then ], [ %1, %if.else ] %.sink11 = phi { i32, i32 } [ %0, %if.then ], [ %1, %if.else ]
%asmresult3 = extractvalue { i32, i32 } %.sink11, 0 %asmresult3 = extractvalue { i32, i32 } %.sink11, 0
%asmresult4 = extractvalue { i32, i32 } %.sink11, 1 %asmresult4 = extractvalue { i32, i32 } %.sink11, 1
%add = add nsw i32 %asmresult4, %asmresult3 %add = add nsw i32 %asmresult4, %asmresult3
br label %return br label %return
label_true: ; preds = %if.else, %if.then label_true: ; preds = %if.else, %if.then
br label %return br label %return
return: ; preds = %if.then, %if.else, %label_true, %if.end return: ; preds = %if.then, %if.else, %label_true, %if.end
%retval.0 = phi i32 [ %add, %if.end ], [ -2, %label_true ], [ -1, %if.else ], [ -1, %if.then ] %retval.0 = phi i32 [ %add, %if.end ], [ -2, %label_true ], [ -1, %if.else ], [ -1, %if.then ]
ret i32 %retval.0 ret i32 %retval.0
} }
define i32 @test3(i1 %cmp) { define i32 @test3(i1 %cmp) nounwind {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: .cfi_offset %esi, -12
; CHECK-NEXT: .cfi_offset %edi, -8
; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: je .LBB2_3 ; CHECK-NEXT: je .LBB2_3
; CHECK-NEXT: # %bb.1: # %true ; CHECK-NEXT: # %bb.1: # %true
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: .short %esi ; CHECK-NEXT: .short %esi
; CHECK-NEXT: .short %edi ; CHECK-NEXT: .short %edi
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: jmp .LBB2_5 ; CHECK-NEXT: jmp .LBB2_5
; CHECK-NEXT: .LBB2_3: # %false ; CHECK-NEXT: .LBB2_3: # %false
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: .short %eax ; CHECK-NEXT: .short %eax
; CHECK-NEXT: .short %edx ; CHECK-NEXT: .short %edx
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: .LBB2_5: # %asm.fallthrough ; CHECK-NEXT: .LBB2_5: # %asm.fallthrough
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB2_6: # Block address taken ; CHECK-NEXT: .LBB2_6: # Block address taken
; CHECK-NEXT: # %indirect ; CHECK-NEXT: # %indirect
; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: jmp .LBB2_5 ; CHECK-NEXT: jmp .LBB2_5
entry: entry:
br i1 %cmp, label %true, label %false br i1 %cmp, label %true, label %false
true: true:
%0 = callbr { i32, i32 } asm sideeffect ".word $0, $1", "={si},={di},!i" () to label %asm.fallthrough [label %indirect] %0 = callbr { i32, i32 } asm sideeffect ".word $0, $1", "={si},={di},!i" () to label %asm.fallthrough [label %indirect]
Show All 34 Lines
; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB3_3: # Block address taken ; CHECK-NEXT: .LBB3_3: # Block address taken
; CHECK-NEXT: # %label_true ; CHECK-NEXT: # %label_true
; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $-2, %eax ; CHECK-NEXT: movl $-2, %eax
; CHECK-NEXT: jmp .LBB3_4 ; CHECK-NEXT: jmp .LBB3_4
entry: entry:
%0 = callbr { i32, i32 } asm sideeffect "testl $0, $0; testl $1, $2; jne ${3:l}", "=r,=r,r,!i,!i,~{dirflag},~{fpsr},~{flags}"(i32 %out1) %0 = callbr { i32, i32 } asm sideeffect "testl $0, $0; testl $1, $2; jne ${3:l}", "=r,=r,r,!i,!i"(i32 %out1)
to label %asm.fallthrough [label %label_true, label %return] to label %asm.fallthrough [label %label_true, label %return]
asm.fallthrough: ; preds = %entry asm.fallthrough: ; preds = %entry
%asmresult = extractvalue { i32, i32 } %0, 0 %asmresult = extractvalue { i32, i32 } %0, 0
%asmresult1 = extractvalue { i32, i32 } %0, 1 %asmresult1 = extractvalue { i32, i32 } %0, 1
%1 = callbr { i32, i32 } asm sideeffect "testl $0, $1; testl $2, $3; jne ${5:l}", "=r,=r,r,r,!i,!i,~{dirflag},~{fpsr},~{flags}"(i32 %asmresult, i32 %asmresult1) %1 = callbr { i32, i32 } asm sideeffect "testl $0, $1; testl $2, $3; jne ${5:l}", "=r,=r,r,r,!i,!i"(i32 %asmresult, i32 %asmresult1)
to label %asm.fallthrough2 [label %label_true, label %return] to label %asm.fallthrough2 [label %label_true, label %return]
asm.fallthrough2: ; preds = %asm.fallthrough asm.fallthrough2: ; preds = %asm.fallthrough
%asmresult3 = extractvalue { i32, i32 } %1, 0 %asmresult3 = extractvalue { i32, i32 } %1, 0
%asmresult4 = extractvalue { i32, i32 } %1, 1 %asmresult4 = extractvalue { i32, i32 } %1, 1
%add = add nsw i32 %asmresult3, %asmresult4 %add = add nsw i32 %asmresult3, %asmresult4
br label %return br label %return
Show All 13 Lines
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB4_1: # Block address taken ; CHECK-NEXT: .LBB4_1: # Block address taken
; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%1 = call i32 @llvm.read_register.i32(metadata !3) %1 = call i32 @llvm.read_register.i32(metadata !3)
%2 = callbr i32 asm "", "={esp},!i,{esp},~{dirflag},~{fpsr},~{flags}"(i32 %1) %2 = callbr i32 asm "", "={esp},!i,{esp}"(i32 %1)
to label %3 [label %4] to label %3 [label %4]
3: 3:
call void @llvm.write_register.i32(metadata !3, i32 %2) call void @llvm.write_register.i32(metadata !3, i32 %2)
br label %4 br label %4
4: 4:
ret void ret void
} }
declare i32 @llvm.read_register.i32(metadata) declare i32 @llvm.read_register.i32(metadata)
declare void @llvm.write_register.i32(metadata, i32) declare void @llvm.write_register.i32(metadata, i32)
!3 = !{!"esp"} !3 = !{!"esp"}