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Differential D137425

[M68k] Add predicates `AtLeastM680x0`
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Authored by 0x59616e on Nov 4 2022, 7:32 AM.

Details

Reviewers
myhsu
Commits
rGc7d6a0f6bfff: [M68k] Replace `IsM680x0` with predicates `AtLeastM680x0`

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Event Timeline

0x59616e created this revision.Nov 4 2022, 7:32 AM
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0x59616e requested review of this revision.Nov 4 2022, 7:32 AM
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0x59616e added a child revision: D136525: [M68k] Add codegen pattern for atomic load / store.Nov 4 2022, 7:33 AM
0x59616e mentioned this in D136525: [M68k] Add codegen pattern for atomic load / store.
Harbormaster completed remote builds in B196143: Diff 473238.Nov 4 2022, 9:03 AM
myhsu added a reviewer: myhsu.Nov 4 2022, 9:19 AM
myhsu added a subscriber: myhsu.
myhsu added inline comments.
llvm/lib/Target/M68k/M68kInstrInfo.td
431–432

Could you remove these IsM680X0 predicates (they're wrong anyway) and refactor their references (there are only a few) to use the new one?

0x59616e updated this revision to Diff 473896.Nov 8 2022, 12:22 AM
0x59616e marked an inline comment as done.

Replace IsM680x0 with AtLeastM680x0

Harbormaster completed remote builds in B196646: Diff 473896.Nov 8 2022, 1:20 AM
myhsu accepted this revision.Nov 8 2022, 6:56 AM

LGTM thanks

This revision is now accepted and ready to land.Nov 8 2022, 6:56 AM
0x59616e added a comment.Nov 9 2022, 2:23 AM

Thanks a lot ;)

Closed by commit rGc7d6a0f6bfff: [M68k] Replace `IsM680x0` with predicates `AtLeastM680x0` (authored by 0x59616e). · Explain WhyNov 9 2022, 2:32 AM
This revision was automatically updated to reflect the committed changes.
0x59616e added a commit: rGc7d6a0f6bfff: [M68k] Replace `IsM680x0` with predicates `AtLeastM680x0`.

Revision Contents

PathSize
llvm/
lib/
Target/
M68k/
4 lines
10 lines

Diff 474205

llvm/lib/Target/M68k/M68kInstrData.td

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/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 /// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
/// -------------------------------------------------- /// --------------------------------------------------
/// | EFFECTIVE ADDRESS /// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 0 1 0 1 1 | MODE | REG /// 0 1 0 0 0 0 1 0 1 1 | MODE | REG
/// -------------------------------------------------- /// --------------------------------------------------
let Uses = [CCR] in { let Uses = [CCR] in {
class MxMoveFromCCR_R class MxMoveFromCCR_R
: MxInst<(outs MxDRD16:$dst), (ins CCRC:$src), "move.w\t$src, $dst", []>, : MxInst<(outs MxDRD16:$dst), (ins CCRC:$src), "move.w\t$src, $dst", []>,
Requires<[ IsM68010 ]> { Requires<[ AtLeastM68010 ]> {
let Inst = (descend 0b0100001011, MxEncAddrMode_d<"dst">.EA); let Inst = (descend 0b0100001011, MxEncAddrMode_d<"dst">.EA);
} }
class MxMoveFromCCR_M<MxOperand MEMOp, MxEncMemOp DST_ENC> class MxMoveFromCCR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
: MxInst<(outs), (ins MEMOp:$dst, CCRC:$src), "move.w\t$src, $dst", []>, : MxInst<(outs), (ins MEMOp:$dst, CCRC:$src), "move.w\t$src, $dst", []>,
Requires<[ IsM68010 ]> { Requires<[ AtLeastM68010 ]> {
let Inst = (ascend let Inst = (ascend
(descend 0b0100001011, DST_ENC.EA), (descend 0b0100001011, DST_ENC.EA),
DST_ENC.Supplement DST_ENC.Supplement
); );
} }
class MxMoveFromCCRPseudo<MxOperand MEMOp> class MxMoveFromCCRPseudo<MxOperand MEMOp>
: MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>; : MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>;
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llvm/lib/Target/M68k/M68kInstrInfo.td

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def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
"TM.getCodeModel() != CodeModel::Kernel">; "TM.getCodeModel() != CodeModel::Kernel">;
def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
"TM.getCodeModel() == CodeModel::Kernel">; "TM.getCodeModel() == CodeModel::Kernel">;
def IsPIC : Predicate<"TM.isPositionIndependent()">; def IsPIC : Predicate<"TM.isPositionIndependent()">;
def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; def IsNotPIC : Predicate<"!TM.isPositionIndependent()">;
def IsM68000 : Predicate<"Subtarget.IsM68000()">;
def IsM68010 : Predicate<"Subtarget.IsM68010()">;
def IsM68020 : Predicate<"Subtarget.IsM68020()">;
def IsM68030 : Predicate<"Subtarget.IsM68030()">;
def IsM68040 : Predicate<"Subtarget.IsM68040()">;
myhsuUnsubmitted
Done
ReplyInline Actions

Could you remove these IsM680X0 predicates (they're wrong anyway) and refactor their references (there are only a few) to use the new one?

myhsu: Could you remove these IsM680X0 predicates (they're wrong anyway) and refactor their references…
def AtLeastM68000 : Predicate<"Subtarget->atLeastM68000()">;
def AtLeastM68010 : Predicate<"Subtarget->atLeastM68010()">;
def AtLeastM68020 : Predicate<"Subtarget->atLeastM68020()">;
def AtLeastM68030 : Predicate<"Subtarget->atLeastM68030()">;
def AtLeastM68040 : Predicate<"Subtarget->atLeastM68040()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Condition Codes // Condition Codes
// //
// These MUST be kept in sync with codes enum in M68kInstrInfo.h // These MUST be kept in sync with codes enum in M68kInstrInfo.h
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def MxCONDt : PatLeaf<(i8 0)>; // True def MxCONDt : PatLeaf<(i8 0)>; // True
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