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Differential D137296

[NFC][AArch64]Precommit test for D135102
ClosedPublic

Authored by mingmingl on Nov 2 2022, 3:46 PM.

Details

Reviewers
dmgreen
fhahn
Commits
rG5d7fdf67f622: [NFC][AArch64]Precommit test for D135102
Summary
  • Run auto updater for 'trunc-to-tbl.ll' and 'build-pair-isel.ll'
  • Add the motivating test of D135102 to 'bitfield-insert.ll'

Diff Detail

Event Timeline

mingmingl created this revision.Nov 2 2022, 3:46 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 2 2022, 3:46 PM
Herald added a subscriber: kristof.beyls. · View Herald Transcript
mingmingl requested review of this revision.Nov 2 2022, 3:46 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 2 2022, 3:46 PM
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mingmingl added a child revision: D135102: [AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection..Nov 2 2022, 3:47 PM
mingmingl added a reviewer: dmgreen.Nov 2 2022, 3:58 PM
mingmingl mentioned this in D135102: [AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection..Nov 2 2022, 4:33 PM
Harbormaster completed remote builds in B195826: Diff 472793.Nov 2 2022, 5:07 PM
fhahn accepted this revision.Nov 3 2022, 6:00 AM
fhahn added a subscriber: fhahn.

LGTM, thanks!

llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
298

nit: stray new line?

361

nit: stray new line?

458

nit: stray new line?

539

nit: stray new line?

This revision is now accepted and ready to land.Nov 3 2022, 6:00 AM
mingmingl updated this revision to Diff 472972.Nov 3 2022, 9:56 AM
mingmingl marked 4 inline comments as done.

Resolve comments.

mingmingl added a comment.Nov 3 2022, 9:56 AM

Thanks!

llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
298

Done (for the other three as well).

These new lines were somehow added by auto-updater so thought I would just keep them.

I removed them just now, and git rebase --continue in D135102 won't re-add it, so going to remove them for now.

Harbormaster completed remote builds in B195955: Diff 472972.Nov 3 2022, 10:44 AM
Closed by commit rG5d7fdf67f622: [NFC][AArch64]Precommit test for D135102 (authored by mingmingl). · Explain WhyNov 3 2022, 10:50 AM
This revision was automatically updated to reflect the committed changes.
mingmingl added a commit: rG5d7fdf67f622: [NFC][AArch64]Precommit test for D135102.
mingmingl removed a child revision: D135102: [AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection..Nov 3 2022, 11:24 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
38 lines
15 lines
480 lines

Diff 472985

llvm/test/CodeGen/AArch64/bitfield-insert.ll

Show First 20 Lines • Show All 595 Lines • ▼ Show 20 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 def $x0
; CHECK-NEXT: ubfiz x0, x0, #7, #8 ; CHECK-NEXT: ubfiz x0, x0, #7, #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = shl i64 %0, 7 %2 = shl i64 %0, 7
%3 = and i64 %2, 32640 ; #0x7f80 %3 = and i64 %2, 32640 ; #0x7f80
ret i64 %3 ret i64 %3
} }
; orr with left-shifted operand is better than bfi, since it improves data
; dependency, and orr has a smaller latency and higher throughput than bfm on
; some AArch64 processors (for the rest, orr is at least as good as bfm)
;
; ubfx x8, x0, #8, #7
; and x9, x0, #0x7f
; orr x0, x9, x8, lsl #7
define i64 @test_orr_not_bfxil_i64(i64 %0) {
; CHECK-LABEL: test_orr_not_bfxil_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: lsr x8, x0, #1
; CHECK-NEXT: and x8, x8, #0x3f80
; CHECK-NEXT: bfxil x8, x0, #0, #7
; CHECK-NEXT: mov x0, x8
; CHECK-NEXT: ret
%2 = and i64 %0, 127
%3 = lshr i64 %0, 1
%4 = and i64 %3, 16256 ; 0x3f80
%5 = or i64 %4, %2
ret i64 %5
}
; The 32-bit test for `test_orr_not_bfxil_i64`.
define i32 @test_orr_not_bfxil_i32(i32 %0) {
; CHECK-LABEL: test_orr_not_bfxil_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, #1
; CHECK-NEXT: and w8, w8, #0x3f80
; CHECK-NEXT: bfxil w8, w0, #0, #7
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: ret
%2 = and i32 %0, 127
%3 = lshr i32 %0, 1
%4 = and i32 %3, 16256 ; 0x3f80
%5 = or i32 %4, %2
ret i32 %5
}

llvm/test/CodeGen/AArch64/build-pair-isel.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 -o - -O0 %s | FileCheck %s ; RUN: llc -mtriple=aarch64 -o - -O0 %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios5.0.0" target triple = "arm64-apple-ios5.0.0"
; This test checks we don't fail isel due to unhandled build_pair nodes. ; This test checks we don't fail isel due to unhandled build_pair nodes.
; CHECK: bfi
define void @compare_and_swap128() { define void @compare_and_swap128() {
; CHECK-LABEL: compare_and_swap128:
; CHECK: // %bb.0:
; CHECK-NEXT: //APP
; CHECK-NEXT: nop
; CHECK-NEXT: //NO_APP
; CHECK-NEXT: // implicit-def: $x9
; CHECK-NEXT: mov w9, w10
; CHECK-NEXT: mov w8, w8
; CHECK-NEXT: // kill: def $x8 killed $w8
; CHECK-NEXT: bfi x8, x9, #32, #32
; CHECK-NEXT: // implicit-def: $x9
; CHECK-NEXT: str x8, [x9]
; CHECK-NEXT: ret
%1 = call i128 asm sideeffect "nop", "=r,~{memory}"() %1 = call i128 asm sideeffect "nop", "=r,~{memory}"()
store i128 %1, i128* undef, align 16 store i128 %1, i128* undef, align 16
ret void ret void
} }

llvm/test/CodeGen/AArch64/trunc-to-tbl.ll

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Linesloop:
%ec = icmp eq i64 %iv.next, 1000 %ec = icmp eq i64 %iv.next, 1000
br i1 %ec, label %loop, label %exit br i1 %ec, label %loop, label %exit
exit: exit:
ret void ret void
} }
define void @trunc_v16i64_to_v16i8_in_loop(ptr %A, ptr %dst) { define void @trunc_v16i64_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-LABEL: trunc_v16i64_to_v16i8_in_loop: ; CHECK-LABEL: trunc_v16i64_to_v16i8_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB3_1: ; %loop ; CHECK-NEXT: LBB3_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8, lsl #7 ; CHECK-NEXT: add x9, x0, x8, lsl #7
; CHECK-NEXT: ldp q3, q2, [x9, #96] ; CHECK-NEXT: ldp q3, q2, [x9, #96]
; CHECK-NEXT: ldp q1, q0, [x9, #32] ; CHECK-NEXT: ldp q1, q0, [x9, #32]
; CHECK-NEXT: uzp1.4s v2, v3, v2 ; CHECK-NEXT: uzp1.4s v2, v3, v2
; CHECK-NEXT: ldp q5, q4, [x9, #64] ; CHECK-NEXT: ldp q5, q4, [x9, #64]
; CHECK-NEXT: uzp1.4s v0, v1, v0 ; CHECK-NEXT: uzp1.4s v0, v1, v0
; CHECK-NEXT: ldp q3, q6, [x9] ; CHECK-NEXT: ldp q3, q6, [x9]
; CHECK-NEXT: uzp1.4s v4, v5, v4 ; CHECK-NEXT: uzp1.4s v4, v5, v4
; CHECK-NEXT: uzp1.8h v2, v4, v2 ; CHECK-NEXT: uzp1.8h v2, v4, v2
; CHECK-NEXT: uzp1.4s v1, v3, v6 ; CHECK-NEXT: uzp1.4s v1, v3, v6
; CHECK-NEXT: uzp1.8h v0, v1, v0 ; CHECK-NEXT: uzp1.8h v0, v1, v0
; CHECK-NEXT: uzp1.16b v0, v0, v2 ; CHECK-NEXT: uzp1.16b v0, v0, v2
; CHECK-NEXT: str q0, [x1, x8, lsl #4] ; CHECK-NEXT: str q0, [x1, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1 ; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000 ; CHECK-NEXT: cmp x8, #1000
; CHECK-NEXT: b.eq LBB3_1 ; CHECK-NEXT: b.eq LBB3_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: trunc_v16i64_to_v16i8_in_loop: ; CHECK-BE-LABEL: trunc_v16i64_to_v16i8_in_loop:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: mov x8, xzr ; CHECK-BE-NEXT: mov x8, xzr
; CHECK-BE-NEXT: .LBB3_1: // %loop ; CHECK-BE-NEXT: .LBB3_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8, lsl #7 ; CHECK-BE-NEXT: add x9, x0, x8, lsl #7
; CHECK-BE-NEXT: add x10, x9, #48 ; CHECK-BE-NEXT: add x10, x9, #48
; CHECK-BE-NEXT: add x11, x9, #32 ; CHECK-BE-NEXT: add x11, x9, #32
; CHECK-BE-NEXT: ld1 { v5.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v5.2d }, [x9]
; CHECK-BE-NEXT: ld1 { v0.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v0.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #80 ; CHECK-BE-NEXT: add x10, x9, #80
; CHECK-BE-NEXT: ld1 { v1.2d }, [x11] ; CHECK-BE-NEXT: ld1 { v1.2d }, [x11]
; CHECK-BE-NEXT: add x11, x9, #112 ; CHECK-BE-NEXT: add x11, x9, #112
; CHECK-BE-NEXT: ld1 { v2.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v2.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #96 ; CHECK-BE-NEXT: add x10, x9, #96
; CHECK-BE-NEXT: ld1 { v3.2d }, [x11] ; CHECK-BE-NEXT: ld1 { v3.2d }, [x11]
; CHECK-BE-NEXT: uzp1 v0.4s, v1.4s, v0.4s ; CHECK-BE-NEXT: uzp1 v0.4s, v1.4s, v0.4s
; CHECK-BE-NEXT: ld1 { v4.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v4.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #64 ; CHECK-BE-NEXT: add x10, x9, #64
; CHECK-BE-NEXT: add x9, x9, #16 ; CHECK-BE-NEXT: add x9, x9, #16
; CHECK-BE-NEXT: ld1 { v6.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v6.2d }, [x10]
; CHECK-BE-NEXT: ld1 { v7.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v7.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, x8, lsl #4 ; CHECK-BE-NEXT: add x9, x1, x8, lsl #4
; CHECK-BE-NEXT: uzp1 v3.4s, v4.4s, v3.4s ; CHECK-BE-NEXT: uzp1 v3.4s, v4.4s, v3.4s
; CHECK-BE-NEXT: add x8, x8, #1 ; CHECK-BE-NEXT: add x8, x8, #1
; CHECK-BE-NEXT: cmp x8, #1000 ; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: uzp1 v2.4s, v6.4s, v2.4s ; CHECK-BE-NEXT: uzp1 v2.4s, v6.4s, v2.4s
; CHECK-BE-NEXT: uzp1 v1.4s, v5.4s, v7.4s ; CHECK-BE-NEXT: uzp1 v1.4s, v5.4s, v7.4s
; CHECK-BE-NEXT: uzp1 v2.8h, v2.8h, v3.8h ; CHECK-BE-NEXT: uzp1 v2.8h, v2.8h, v3.8h
; CHECK-BE-NEXT: uzp1 v0.8h, v1.8h, v0.8h ; CHECK-BE-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-BE-NEXT: uzp1 v0.16b, v0.16b, v2.16b ; CHECK-BE-NEXT: uzp1 v0.16b, v0.16b, v2.16b
; CHECK-BE-NEXT: st1 { v0.16b }, [x9] ; CHECK-BE-NEXT: st1 { v0.16b }, [x9]
; CHECK-BE-NEXT: b.eq .LBB3_1 ; CHECK-BE-NEXT: b.eq .LBB3_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
fhahnUnsubmitted
Done
ReplyInline Actions

nit: stray new line?

fhahn: nit: stray new line?
mingminglAuthorUnsubmitted
Done
ReplyInline Actions

Done (for the other three as well).

These new lines were somehow added by auto-updater so thought I would just keep them.

I removed them just now, and git rebase --continue in D135102 won't re-add it, so going to remove them for now.

mingmingl: Done (for the other three as well). These new lines were somehow added by auto-updater so…
entry: entry:
br label %loop br label %loop
loop: loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%gep.A = getelementptr inbounds <16 x i64>, ptr %A, i64 %iv %gep.A = getelementptr inbounds <16 x i64>, ptr %A, i64 %iv
%l.A = load <16 x i64>, ptr %gep.A %l.A = load <16 x i64>, ptr %gep.A
%trunc = trunc <16 x i64> %l.A to <16 x i8> %trunc = trunc <16 x i64> %l.A to <16 x i8>
%gep.dst = getelementptr inbounds <16 x i8>, ptr %dst, i64 %iv %gep.dst = getelementptr inbounds <16 x i8>, ptr %dst, i64 %iv
store <16 x i8> %trunc, ptr %gep.dst store <16 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1 %iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000 %ec = icmp eq i64 %iv.next, 1000
br i1 %ec, label %loop, label %exit br i1 %ec, label %loop, label %exit
exit: exit:
ret void ret void
} }
define void @trunc_v8i64_to_v8i8_in_loop(ptr %A, ptr %dst) { define void @trunc_v8i64_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-LABEL: trunc_v8i64_to_v8i8_in_loop: ; CHECK-LABEL: trunc_v8i64_to_v8i8_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB4_1: ; %loop ; CHECK-NEXT: LBB4_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8, lsl #6 ; CHECK-NEXT: add x9, x0, x8, lsl #6
; CHECK-NEXT: ldp q1, q0, [x9, #32] ; CHECK-NEXT: ldp q1, q0, [x9, #32]
; CHECK-NEXT: ldp q3, q2, [x9] ; CHECK-NEXT: ldp q3, q2, [x9]
; CHECK-NEXT: uzp1.4s v0, v1, v0 ; CHECK-NEXT: uzp1.4s v0, v1, v0
; CHECK-NEXT: uzp1.4s v1, v3, v2 ; CHECK-NEXT: uzp1.4s v1, v3, v2
; CHECK-NEXT: uzp1.8h v0, v1, v0 ; CHECK-NEXT: uzp1.8h v0, v1, v0
; CHECK-NEXT: xtn.8b v0, v0 ; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: str d0, [x1, x8, lsl #3] ; CHECK-NEXT: str d0, [x1, x8, lsl #3]
; CHECK-NEXT: add x8, x8, #1 ; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000 ; CHECK-NEXT: cmp x8, #1000
; CHECK-NEXT: b.eq LBB4_1 ; CHECK-NEXT: b.eq LBB4_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: trunc_v8i64_to_v8i8_in_loop: ; CHECK-BE-LABEL: trunc_v8i64_to_v8i8_in_loop:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: mov x8, xzr ; CHECK-BE-NEXT: mov x8, xzr
; CHECK-BE-NEXT: .LBB4_1: // %loop ; CHECK-BE-NEXT: .LBB4_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8, lsl #6 ; CHECK-BE-NEXT: add x9, x0, x8, lsl #6
; CHECK-BE-NEXT: add x10, x9, #48 ; CHECK-BE-NEXT: add x10, x9, #48
; CHECK-BE-NEXT: ld1 { v1.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v1.2d }, [x9]
; CHECK-BE-NEXT: ld1 { v0.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v0.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #32 ; CHECK-BE-NEXT: add x10, x9, #32
; CHECK-BE-NEXT: add x9, x9, #16 ; CHECK-BE-NEXT: add x9, x9, #16
; CHECK-BE-NEXT: ld1 { v2.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v2.2d }, [x10]
; CHECK-BE-NEXT: ld1 { v3.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v3.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, x8, lsl #3 ; CHECK-BE-NEXT: add x9, x1, x8, lsl #3
; CHECK-BE-NEXT: add x8, x8, #1 ; CHECK-BE-NEXT: add x8, x8, #1
; CHECK-BE-NEXT: cmp x8, #1000 ; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: uzp1 v0.4s, v2.4s, v0.4s ; CHECK-BE-NEXT: uzp1 v0.4s, v2.4s, v0.4s
; CHECK-BE-NEXT: uzp1 v1.4s, v1.4s, v3.4s ; CHECK-BE-NEXT: uzp1 v1.4s, v1.4s, v3.4s
; CHECK-BE-NEXT: uzp1 v0.8h, v1.8h, v0.8h ; CHECK-BE-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-BE-NEXT: xtn v0.8b, v0.8h ; CHECK-BE-NEXT: xtn v0.8b, v0.8h
; CHECK-BE-NEXT: st1 { v0.8b }, [x9] ; CHECK-BE-NEXT: st1 { v0.8b }, [x9]
; CHECK-BE-NEXT: b.eq .LBB4_1 ; CHECK-BE-NEXT: b.eq .LBB4_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
fhahnUnsubmitted
Done
ReplyInline Actions

nit: stray new line?

fhahn: nit: stray new line?
entry: entry:
br label %loop br label %loop
loop: loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%gep.A = getelementptr inbounds <8 x i64>, ptr %A, i64 %iv %gep.A = getelementptr inbounds <8 x i64>, ptr %A, i64 %iv
%l.A = load <8 x i64>, ptr %gep.A %l.A = load <8 x i64>, ptr %gep.A
%trunc = trunc <8 x i64> %l.A to <8 x i8> %trunc = trunc <8 x i64> %l.A to <8 x i8>
%gep.dst = getelementptr inbounds <8 x i8>, ptr %dst, i64 %iv %gep.dst = getelementptr inbounds <8 x i8>, ptr %dst, i64 %iv
store <8 x i8> %trunc, ptr %gep.dst store <8 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1 %iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000 %ec = icmp eq i64 %iv.next, 1000
br i1 %ec, label %loop, label %exit br i1 %ec, label %loop, label %exit
exit: exit:
ret void ret void
} }
define void @trunc_v8i19_to_v8i8_in_loop(ptr %A, ptr %dst) { define void @trunc_v8i19_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-LABEL: trunc_v8i19_to_v8i8_in_loop: ; CHECK-LABEL: trunc_v8i19_to_v8i8_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB5_1: ; %loop ; CHECK-NEXT: LBB5_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldp x10, x9, [x0] ; CHECK-NEXT: ldp x10, x9, [x0]
; CHECK-NEXT: ldrb w11, [x0, #18] ; CHECK-NEXT: ldrb w11, [x0, #18]
; CHECK-NEXT: ldrh w13, [x0, #16] ; CHECK-NEXT: ldrh w13, [x0, #16]
; CHECK-NEXT: add x0, x0, #32 ; CHECK-NEXT: add x0, x0, #32
; CHECK-NEXT: lsr x14, x10, #19 ; CHECK-NEXT: lsr x14, x10, #19
; CHECK-NEXT: fmov s0, w10 ; CHECK-NEXT: fmov s0, w10
; CHECK-NEXT: ubfx x12, x9, #12, #20 ; CHECK-NEXT: ubfx x12, x9, #12, #20
; CHECK-NEXT: lsr x15, x9, #31 ; CHECK-NEXT: lsr x15, x9, #31
; CHECK-NEXT: bfi w13, w11, #16, #8 ; CHECK-NEXT: bfi w13, w11, #16, #8
; CHECK-NEXT: lsr x11, x9, #50 ; CHECK-NEXT: lsr x11, x9, #50
; CHECK-NEXT: mov.s v0[1], w14 ; CHECK-NEXT: mov.s v0[1], w14
; CHECK-NEXT: fmov s1, w12 ; CHECK-NEXT: fmov s1, w12
; CHECK-NEXT: lsr x12, x10, #38 ; CHECK-NEXT: lsr x12, x10, #38
; CHECK-NEXT: bfi w11, w13, #14, #18 ; CHECK-NEXT: bfi w11, w13, #14, #18
; CHECK-NEXT: lsr x10, x10, #57 ; CHECK-NEXT: lsr x10, x10, #57
; CHECK-NEXT: bfi w10, w9, #7, #25 ; CHECK-NEXT: bfi w10, w9, #7, #25
; CHECK-NEXT: lsr w9, w13, #5 ; CHECK-NEXT: lsr w9, w13, #5
; CHECK-NEXT: mov.s v1[1], w15 ; CHECK-NEXT: mov.s v1[1], w15
; CHECK-NEXT: mov.s v0[2], w12 ; CHECK-NEXT: mov.s v0[2], w12
; CHECK-NEXT: mov.s v1[2], w11 ; CHECK-NEXT: mov.s v1[2], w11
; CHECK-NEXT: mov.s v0[3], w10 ; CHECK-NEXT: mov.s v0[3], w10
; CHECK-NEXT: mov.s v1[3], w9 ; CHECK-NEXT: mov.s v1[3], w9
; CHECK-NEXT: uzp1.8h v0, v0, v1 ; CHECK-NEXT: uzp1.8h v0, v0, v1
; CHECK-NEXT: xtn.8b v0, v0 ; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: str d0, [x1, x8, lsl #3] ; CHECK-NEXT: str d0, [x1, x8, lsl #3]
; CHECK-NEXT: add x8, x8, #1 ; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000 ; CHECK-NEXT: cmp x8, #1000
; CHECK-NEXT: b.eq LBB5_1 ; CHECK-NEXT: b.eq LBB5_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: trunc_v8i19_to_v8i8_in_loop: ; CHECK-BE-LABEL: trunc_v8i19_to_v8i8_in_loop:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: mov x8, xzr ; CHECK-BE-NEXT: mov x8, xzr
; CHECK-BE-NEXT: .LBB5_1: // %loop ; CHECK-BE-NEXT: .LBB5_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: ldp x10, x9, [x0] ; CHECK-BE-NEXT: ldp x10, x9, [x0]
; CHECK-BE-NEXT: ldrh w15, [x0, #16] ; CHECK-BE-NEXT: ldrh w15, [x0, #16]
; CHECK-BE-NEXT: lsr x12, x10, #40 ; CHECK-BE-NEXT: lsr x12, x10, #40
; CHECK-BE-NEXT: lsr x13, x10, #45 ; CHECK-BE-NEXT: lsr x13, x10, #45
; CHECK-BE-NEXT: lsr x11, x9, #40 ; CHECK-BE-NEXT: lsr x11, x9, #40
; CHECK-BE-NEXT: ubfx x14, x9, #33, #7 ; CHECK-BE-NEXT: ubfx x14, x9, #33, #7
; CHECK-BE-NEXT: ubfx x16, x10, #26, #14 ; CHECK-BE-NEXT: ubfx x16, x10, #26, #14
; CHECK-BE-NEXT: bfi w16, w12, #14, #18 ; CHECK-BE-NEXT: bfi w16, w12, #14, #18
; CHECK-BE-NEXT: ubfx x12, x9, #14, #18 ; CHECK-BE-NEXT: ubfx x12, x9, #14, #18
; CHECK-BE-NEXT: bfi w14, w11, #7, #24 ; CHECK-BE-NEXT: bfi w14, w11, #7, #24
; CHECK-BE-NEXT: ldrb w11, [x0, #18] ; CHECK-BE-NEXT: ldrb w11, [x0, #18]
; CHECK-BE-NEXT: fmov s0, w13 ; CHECK-BE-NEXT: fmov s0, w13
; CHECK-BE-NEXT: add x0, x0, #32 ; CHECK-BE-NEXT: add x0, x0, #32
; CHECK-BE-NEXT: fmov s1, w14 ; CHECK-BE-NEXT: fmov s1, w14
; CHECK-BE-NEXT: bfi w11, w15, #8, #16 ; CHECK-BE-NEXT: bfi w11, w15, #8, #16
; CHECK-BE-NEXT: mov v0.s[1], w16 ; CHECK-BE-NEXT: mov v0.s[1], w16
; CHECK-BE-NEXT: mov v1.s[1], w12 ; CHECK-BE-NEXT: mov v1.s[1], w12
; CHECK-BE-NEXT: extr x12, x10, x9, #40 ; CHECK-BE-NEXT: extr x12, x10, x9, #40
; CHECK-BE-NEXT: lsl x9, x9, #24 ; CHECK-BE-NEXT: lsl x9, x9, #24
; CHECK-BE-NEXT: ubfx x10, x10, #7, #25 ; CHECK-BE-NEXT: ubfx x10, x10, #7, #25
; CHECK-BE-NEXT: orr w9, w11, w9 ; CHECK-BE-NEXT: orr w9, w11, w9
; CHECK-BE-NEXT: lsr w9, w9, #19 ; CHECK-BE-NEXT: lsr w9, w9, #19
; CHECK-BE-NEXT: mov v0.s[2], w10 ; CHECK-BE-NEXT: mov v0.s[2], w10
; CHECK-BE-NEXT: ubfx x10, x12, #12, #20 ; CHECK-BE-NEXT: ubfx x10, x12, #12, #20
; CHECK-BE-NEXT: mov v1.s[2], w9 ; CHECK-BE-NEXT: mov v1.s[2], w9
; CHECK-BE-NEXT: add x9, x1, x8, lsl #3 ; CHECK-BE-NEXT: add x9, x1, x8, lsl #3
; CHECK-BE-NEXT: add x8, x8, #1 ; CHECK-BE-NEXT: add x8, x8, #1
; CHECK-BE-NEXT: mov v0.s[3], w10 ; CHECK-BE-NEXT: mov v0.s[3], w10
; CHECK-BE-NEXT: cmp x8, #1000 ; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: mov v1.s[3], w11 ; CHECK-BE-NEXT: mov v1.s[3], w11
; CHECK-BE-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-BE-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-BE-NEXT: xtn v0.8b, v0.8h ; CHECK-BE-NEXT: xtn v0.8b, v0.8h
; CHECK-BE-NEXT: st1 { v0.8b }, [x9] ; CHECK-BE-NEXT: st1 { v0.8b }, [x9]
; CHECK-BE-NEXT: b.eq .LBB5_1 ; CHECK-BE-NEXT: b.eq .LBB5_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
fhahnUnsubmitted
Done
ReplyInline Actions

nit: stray new line?

fhahn: nit: stray new line?
entry: entry:
br label %loop br label %loop
loop: loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%gep.A = getelementptr inbounds <8 x i19>, ptr %A, i64 %iv %gep.A = getelementptr inbounds <8 x i19>, ptr %A, i64 %iv
%l.A = load <8 x i19>, ptr %gep.A %l.A = load <8 x i19>, ptr %gep.A
%trunc = trunc <8 x i19> %l.A to <8 x i8> %trunc = trunc <8 x i19> %l.A to <8 x i8>
%gep.dst = getelementptr inbounds <8 x i8>, ptr %dst, i64 %iv %gep.dst = getelementptr inbounds <8 x i8>, ptr %dst, i64 %iv
store <8 x i8> %trunc, ptr %gep.dst store <8 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1 %iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000 %ec = icmp eq i64 %iv.next, 1000
br i1 %ec, label %loop, label %exit br i1 %ec, label %loop, label %exit
exit: exit:
ret void ret void
} }
define void @trunc_v11i64_to_v11i8_in_loop(ptr %A, ptr %dst) { define void @trunc_v11i64_to_v11i8_in_loop(ptr %A, ptr %dst) {
; CHECK-LABEL: trunc_v11i64_to_v11i8_in_loop: ; CHECK-LABEL: trunc_v11i64_to_v11i8_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov w8, #1000 ; CHECK-NEXT: mov w8, #1000
; CHECK-NEXT: LBB6_1: ; %loop ; CHECK-NEXT: LBB6_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ldp q1, q0, [x0, #32]
; CHECK-NEXT: add x9, x1, #8 ; CHECK-NEXT: add x9, x1, #8
; CHECK-NEXT: add x10, x1, #10 ; CHECK-NEXT: add x10, x1, #10
; CHECK-NEXT: subs x8, x8, #1 ; CHECK-NEXT: subs x8, x8, #1
; CHECK-NEXT: ldp q3, q2, [x0] ; CHECK-NEXT: ldp q3, q2, [x0]
; CHECK-NEXT: uzp1.4s v0, v1, v0 ; CHECK-NEXT: uzp1.4s v0, v1, v0
; CHECK-NEXT: ldr d4, [x0, #80] ; CHECK-NEXT: ldr d4, [x0, #80]
; CHECK-NEXT: ldr q1, [x0, #64] ; CHECK-NEXT: ldr q1, [x0, #64]
; CHECK-NEXT: add x0, x0, #128 ; CHECK-NEXT: add x0, x0, #128
; CHECK-NEXT: uzp1.4s v2, v3, v2 ; CHECK-NEXT: uzp1.4s v2, v3, v2
; CHECK-NEXT: uzp1.4s v1, v1, v4 ; CHECK-NEXT: uzp1.4s v1, v1, v4
; CHECK-NEXT: uzp1.8h v0, v2, v0 ; CHECK-NEXT: uzp1.8h v0, v2, v0
; CHECK-NEXT: xtn.4h v1, v1 ; CHECK-NEXT: xtn.4h v1, v1
; CHECK-NEXT: uzp1.16b v0, v0, v1 ; CHECK-NEXT: uzp1.16b v0, v0, v1
; CHECK-NEXT: xtn.8b v1, v1 ; CHECK-NEXT: xtn.8b v1, v1
; CHECK-NEXT: st1.b { v1 }[2], [x10] ; CHECK-NEXT: st1.b { v1 }[2], [x10]
; CHECK-NEXT: str d0, [x1], #16 ; CHECK-NEXT: str d0, [x1], #16
; CHECK-NEXT: st1.h { v0 }[4], [x9] ; CHECK-NEXT: st1.h { v0 }[4], [x9]
; CHECK-NEXT: b.eq LBB6_1 ; CHECK-NEXT: b.eq LBB6_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: trunc_v11i64_to_v11i8_in_loop: ; CHECK-BE-LABEL: trunc_v11i64_to_v11i8_in_loop:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: mov w8, #1000 ; CHECK-BE-NEXT: mov w8, #1000
; CHECK-BE-NEXT:.LBB6_1: // %loop ; CHECK-BE-NEXT: .LBB6_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, #48 ; CHECK-BE-NEXT: add x9, x0, #48
; CHECK-BE-NEXT: add x10, x0, #32 ; CHECK-BE-NEXT: add x10, x0, #32
; CHECK-BE-NEXT: ld1 { v0.2d }, [x0] ; CHECK-BE-NEXT: ld1 { v0.2d }, [x0]
; CHECK-BE-NEXT: subs x8, x8, #1 ; CHECK-BE-NEXT: subs x8, x8, #1
; CHECK-BE-NEXT: ld1 { v1.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v1.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #16 ; CHECK-BE-NEXT: add x9, x0, #16
; CHECK-BE-NEXT: ld1 { v2.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v2.2d }, [x10]
; CHECK-BE-NEXT: add x10, x0, #64 ; CHECK-BE-NEXT: add x10, x0, #64
; CHECK-BE-NEXT: ld1 { v3.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v3.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #10 ; CHECK-BE-NEXT: add x9, x1, #10
; CHECK-BE-NEXT: ld1 { v4.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v4.2d }, [x10]
; CHECK-BE-NEXT: add x10, x1, #8 ; CHECK-BE-NEXT: add x10, x1, #8
; CHECK-BE-NEXT: uzp1 v1.4s, v2.4s, v1.4s ; CHECK-BE-NEXT: uzp1 v1.4s, v2.4s, v1.4s
; CHECK-BE-NEXT: ldr d2, [x0, #80] ; CHECK-BE-NEXT: ldr d2, [x0, #80]
; CHECK-BE-NEXT: add x0, x0, #128 ; CHECK-BE-NEXT: add x0, x0, #128
; CHECK-BE-NEXT: uzp1 v0.4s, v0.4s, v3.4s ; CHECK-BE-NEXT: uzp1 v0.4s, v0.4s, v3.4s
; CHECK-BE-NEXT: uzp1 v2.4s, v4.4s, v2.4s ; CHECK-BE-NEXT: uzp1 v2.4s, v4.4s, v2.4s
; CHECK-BE-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-BE-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-BE-NEXT: xtn v1.4h, v2.4s ; CHECK-BE-NEXT: xtn v1.4h, v2.4s
; CHECK-BE-NEXT: uzp1 v0.16b, v0.16b, v1.16b ; CHECK-BE-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-BE-NEXT: xtn v1.8b, v1.8h ; CHECK-BE-NEXT: xtn v1.8b, v1.8h
; CHECK-BE-NEXT: st1 { v1.b }[2], [x9] ; CHECK-BE-NEXT: st1 { v1.b }[2], [x9]
; CHECK-BE-NEXT: rev64 v2.16b, v0.16b ; CHECK-BE-NEXT: rev64 v2.16b, v0.16b
; CHECK-BE-NEXT: rev16 v0.16b, v0.16b ; CHECK-BE-NEXT: rev16 v0.16b, v0.16b
; CHECK-BE-NEXT: str d2, [x1], #16 ; CHECK-BE-NEXT: str d2, [x1], #16
; CHECK-BE-NEXT: st1 { v0.h }[4], [x10] ; CHECK-BE-NEXT: st1 { v0.h }[4], [x10]
; CHECK-BE-NEXT: b.eq .LBB6_1 ; CHECK-BE-NEXT: b.eq .LBB6_1
; CHECK-BE-NEXT:// %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
fhahnUnsubmitted
Done
ReplyInline Actions

nit: stray new line?

fhahn: nit: stray new line?
entry: entry:
br label %loop br label %loop
loop: loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%gep.A = getelementptr inbounds <11 x i64>, ptr %A, i64 %iv %gep.A = getelementptr inbounds <11 x i64>, ptr %A, i64 %iv
%l.A = load <11 x i64>, ptr %gep.A %l.A = load <11 x i64>, ptr %gep.A
%trunc = trunc <11 x i64> %l.A to <11 x i8> %trunc = trunc <11 x i64> %l.A to <11 x i8>
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