Introduce predicate for a atomic operations in GMIR

[sameerds]

llvm/include/llvm/Support/TargetOpcodes.def

395

Why is this marker needed? Should OP_END be sufficient to pair with OP_START?

[yassingh]

llvm/include/llvm/Support/TargetOpcodes.def

395

Yes it's not, OP_START and OP_END should be sufficient, will update

[yassingh]

Removed extra markers

[arsenm]

What's this going to be used for?

llvm/include/llvm/Support/TargetOpcodes.def

395

Why doesn't G_FENCE count?

[yassingh]

In D134266#3802636, @arsenm wrote:

What's this going to be used for?

Atomic instructions are inherently divergent, uniformity analysis need to identify these instructions to mark them divergent

[yassingh]

llvm/include/llvm/Support/TargetOpcodes.def

395

I have a doubt too, could not find details about this instruction. Should this also be included?

[arsenm]

I don't know how much use a general "isAtomic" predicate will be. You wouldn't really do anything with the same operand indices for all of them. An isAtomicRMW would be more useful?

[arsenm]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

114

Opc >= START?

[sameerds]

In D134266#3804612, @arsenm wrote:

I don't know how much use a general "isAtomic" predicate will be. You wouldn't really do anything with the same operand indices for all of them. An isAtomicRMW would be more useful?

It will need to be "isAtomicRead" to include AtomicLoad and AtomicRMW. Basically any atomic operation that returns a value. We assume that by its very nature of being atomic, the returned value can be different in each thread. Fence is not relevant for this use-case since it does not access memory or return anything; it merely orders operations within the same thread.

[yassingh]

Updated the predicate to check isAtomicRMW operations, added another one for CMPXCGH

[arsenm]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

118–121

I think the benefit of this one is dubious. They don't have the same operand structure

[yassingh]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

118–121

We need this to check divergence of an instruction in GMIR, it was either this or moving this opcode matching inside isDivergent type function which didn't look right and also wasn't consistent with how Atomic instructions are handled in IR divergence/uniformity analysis.

[arsenm]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

118–121

There's nothing wrong with just checking opcodes where you need to. The IR and MIR aren't structured exactly the same way

[yassingh]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

118–121

There's nothing wrong with just checking opcodes where you need to. The IR and MIR aren't structured exactly the same way

Okay. I'll get rid of the second predicate, maybe when the divergence revision comes up we can revisit this if that doesn't look right

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   TargetInstrInfo(const TargetInstrInfo &) = delete;
   TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
   virtual ~TargetInstrInfo();
 
   static bool isGenericOpcode(unsigned Opc) {
     return Opc <= TargetOpcode::GENERIC_OP_END;
   }
 
+  static bool isGenericAtomicOpcode(unsigned Opc) {
+    return TargetOpcode::GENERIC_ATOMIC_OP_START <= Opc &&
+           Opc <= TargetOpcode::GENERIC_ATOMIC_OP_END;
+  }
+
   /// Given a machine instruction descriptor, returns the register
   /// class constraint for OpNum, or NULL.
   virtual
   const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
                                          const TargetRegisterInfo *TRI,
                                          const MachineFunction &MF) const;
 
   /// Return true if the instruction is trivially rematerializable, meaning it
   /// has no side effects and requires no operands that aren't always available.
   /// This means the only allowed uses are constants and unallocatable physical
   /// registers so that the instructions result is independent of the place
   /// in the function.

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN)
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX)
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN)
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD)
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB)
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX)
 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN)
 
+// Marker for start of Generic Atomic opcodes
+HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_ATOMIC_OPCODE_START, G_ATOMIC_CMPXCHG_WITH_SUCCESS)
+HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMIC_OP_START, PRE_ISEL_GENERIC_ATOMIC_OPCODE_START)
+
+// Marker of end of Generic Atomic opcodes
+HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_ATOMIC_OPCODE_END, G_ATOMICRMW_FMIN)
+HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMIC_OP_END, PRE_ISEL_GENERIC_ATOMIC_OPCODE_END)
+
 // Generic atomic fence
 HANDLE_TARGET_OPCODE(G_FENCE)
 
 /// Generic conditional branch instruction.
 HANDLE_TARGET_OPCODE(G_BRCOND)
 
 /// Generic indirect branch instruction.
 HANDLE_TARGET_OPCODE(G_BRINDIRECT)