[Lanai] Fix useDeprecatedPositionallyEncodedOperands errors.

[jyknight]

Summary

This is a follow-on to https://reviews.llvm.org/D134073.

Lanai was almost clean: the only issue is that 'bit' behaves
differently than 'bits<1>', because only the 'bits' type preserves
unresolved references via 'keepUnsetBits()' in
TableGen/Record.h. Thus, use bits instead.

This issue _would_ have caused invalid instruction emission/decoding,
except that the PQ bits were being overriden after the fact by code in
'adjustPqBits' in MCTargetDesc/LanaiMCCodeEmitter.cpp, and
'PostOperandDecodeAdjust' in Disassembler/LanaiDisassembler.cpp.

[jpienaar]

Thanks!

llvm/lib/Target/Lanai/Lanai.td

 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "LanaiSchedule.td"
 include "LanaiRegisterInfo.td"
 include "LanaiCallingConv.td"
 include "LanaiInstrInfo.td"
 
-def LanaiInstrInfo : InstrInfo {
-  let useDeprecatedPositionallyEncodedOperands = 1;
-}
+def LanaiInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Lanai processors supported.
 //===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic", LanaiSchedModel, []>;
 def : ProcessorModel<"v11", LanaiSchedModel, []>;
 

llvm/lib/Target/Lanai/LanaiInstrFormats.td

 //
 // The constant is sign-extended for this instruction.
 //
 // A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots.
 class InstRM<bit S, dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstLanai<outs, ins, asmstr, pattern> {
   bits<5> Rd;
   bits<5> Rs1;
-  bit P;
-  bit Q;
+  bits<1> P;
+  bits<1> Q;
   bits<16> imm16;
   // Dummy variables to allow multiclass definition of RM and RRM
   bits<2> YL;
   bit E;
 
   let Opcode{3 - 1} = 0b100;
   let Opcode{0} = S;
   let Inst{27 - 23} = Rd;

 //
 // A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots.
 class InstRRM<bit S, dag outs, dag ins, string asmstr,
               list<dag> pattern>
     : InstLanai<outs, ins, asmstr, pattern> {
   bits<5> Rd;
   bits<5> Rs1;
   bits<5> Rs2;
-  bit P;
-  bit Q;
+  bits<1> P;
+  bits<1> Q;
   bits<3> BBB;
   bits<5> JJJJJ;
   bits<2> YL;
   bit E;
 
   let Opcode{3 - 1} = 0b101;
   let Opcode{0} = S;
   let Inst{27 - 23} = Rd;
class InstSPLS<dag outs, dag ins, string asmstr,
                list<dag> pattern>
     : InstLanai<outs, ins, asmstr, pattern> {
   bits<5> Rd;
   bits<5> Rs1;
   bits<5> msb;
   bit Y;
   bit S;
   bit E;
-  bit P;
-  bit Q;
+  bits<1> P;
+  bits<1> Q;
   bits<10> imm10;
 
   let Opcode = 0b1111;
   let Inst{27 - 23} = Rd;
   let Inst{22 - 18} = Rs1;
   let Inst{17 - 15} = 0b110;
   let Inst{14} = Y;
   let Inst{13} = S;