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Differential D132277

[NFC] Move a test case across files.
ClosedPublic

Authored by mingmingl on Aug 19 2022, 9:18 PM.

Details

Reviewers
dmgreen
efriedma
Commits
rG4df696fbe9ae: [NFC] Move a test case across files.
Summary

The test case is about pmull2 instruction generated used than a SIMD
ldr being generated. So aarch64-pmull2.ll is a better test file.

Diff Detail

Event Timeline

mingmingl created this revision.Aug 19 2022, 9:18 PM
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mingmingl requested review of this revision.Aug 19 2022, 9:18 PM
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Harbormaster completed remote builds in B182336: Diff 454160.Aug 19 2022, 10:04 PM
efriedma accepted this revision.Aug 30 2022, 1:05 PM

LGTM

This revision is now accepted and ready to land.Aug 30 2022, 1:05 PM
mingmingl added a comment.Aug 30 2022, 2:17 PM

thanks! going to submit this.

This revision was landed with ongoing or failed builds.Aug 30 2022, 2:18 PM
Closed by commit rG4df696fbe9ae: [NFC] Move a test case across files. (authored by mingmingl). · Explain Why
This revision was automatically updated to reflect the committed changes.
mingmingl added a commit: rG4df696fbe9ae: [NFC] Move a test case across files..

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
15 lines
15 lines

Diff 456795

llvm/test/CodeGen/AArch64/aarch64-pmull2.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%4 = extractelement <2 x i64> %1, i64 1 %4 = extractelement <2 x i64> %1, i64 1
%5 = extractelement <2 x i64> %2, i64 0 %5 = extractelement <2 x i64> %2, i64 0
%6 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %5) %6 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %5)
store <16 x i8> %6, ptr %0, align 16 store <16 x i8> %6, ptr %0, align 16
ret void ret void
} }
; Operand %4 is the higher-half of v2i64, and operand %2 is an input parameter of i64.
; Test that %2 is duplicated into the proper lane of SIMD directly for optimal codegen.
define void @test3(ptr %0, <2 x i64> %1, i64 %2) {
; CHECK-LABEL: test3:
; CHECK: // %bb.0:
; CHECK-NEXT: dup v1.2d, x1
; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%4 = extractelement <2 x i64> %1, i64 1
%5 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %2)
store <16 x i8> %5, ptr %0, align 16
ret void
}
declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)

llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1 %5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1
%6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1 %6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1
%7 = load i64, ptr %6, align 8 %7 = load i64, ptr %6, align 8
%8 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %7, i64 %3) %8 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %7, i64 %3)
store <16 x i8> %8, ptr %5, align 16 store <16 x i8> %8, ptr %5, align 16
ret void ret void
} }
; Operand %4 is the higher-half of v2i64, and operand %2 is an input parameter of i64.
; Test that %2 is duplicated into the proper lane of SIMD directly for optimal codegen.
define void @test4(ptr %0, <2 x i64> %1, i64 %2) {
; CHECK-LABEL: test4:
; CHECK: // %bb.0:
; CHECK-NEXT: dup v1.2d, x1
; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%4 = extractelement <2 x i64> %1, i64 1
%5 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %2)
store <16 x i8> %5, ptr %0, align 16
ret void
}
declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)