[GlobalStatus] Handle masked load intrinsics as special loads

[TiehuZhang]

Summary

GlobalOpt does not optimize global variables used by calls, even for masked load intrinsics. This patch treats masked load intrinsics as special loads so that global variables used by such calls can also be optimized later.

llvm/lib/Transforms/Utils/GlobalStatus.cpp

if (const Constant *C = dyn_cast<Constant>(UR)) {
         if (MTI->getArgOperand(1) == V)
           GS.IsLoaded = true;
       } else if (const MemSetInst *MSI = dyn_cast<MemSetInst>(I)) {
         assert(MSI->getArgOperand(0) == V && "Memset only takes one pointer!");
         if (MSI->isVolatile())
           return true;
         GS.StoredType = GlobalStatus::Stored;
       } else if (const auto *CB = dyn_cast<CallBase>(I)) {
+        const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
+        if (II && II->getIntrinsicID() == Intrinsic::masked_load) {
+          if (II->isVolatile())
+            return true;
+          GS.Ordering =
+              strongerOrdering(GS.Ordering, AtomicOrdering::NotAtomic);
+        } else {
           if (!CB->isCallee(&U))
             return true;
           GS.IsLoaded = true;
+        }
       } else {
         return true; // Any other non-load instruction might take address!
       }
     } else {
       // Otherwise must be some other user.
       return true;
     }
   }

llvm/test/Transforms/GlobalOpt/masked-load-global.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -globalopt -S < %s -o - | FileCheck %s
 
 @lPtr = internal unnamed_addr constant [16 x i32] [i32 7, i32 15, i32 10, i32 10, i32 6, i32 10, i32 8, i32 11, i32 11, i32 14, i32 12, i32 2, i32 9, i32 14, i32 2, i32 11], align 4
 @uPtr = internal unnamed_addr constant [16 x i32] [i32 0, i32 7, i32 10, i32 9, i32 7, i32 4, i32 11, i32 10, i32 9, i32 11, i32 4, i32 6, i32 15, i32 2, i32 13, i32 7], align 4
 @upperPtr = internal unnamed_addr constant [16 x double] [double 5.000000e-01, double 1.250000e-01, double 5.000000e-01, double 1.250000e-01, double 5.000000e-01, double 9.091000e-02, double 2.500000e-01, double 7.692000e-02, double 1.111100e-01, double 6.250000e-02, double 0x3FB11148FD9FD36F, double 5.000000e-01, double 0x3FB2493C89F40A28, double 1.000000e+00, double 7.692000e-02, double 0x3FB11148FD9FD36F], align 8
 @lowerPtr = internal unnamed_addr constant [16 x double] [double 1.111100e-01, double 1.250000e-01, double 1.250000e-01, double 6.250000e-02, double 8.333000e-02, double 3.333300e-01, double 1.000000e-01, double 2.000000e-01, double 0x3FB2493C89F40A28, double 0x3FB2493C89F40A28, double 9.091000e-02, double 7.692000e-02, double 6.250000e-02, double 1.250000e-01, double 2.500000e-01, double 5.000000e-01], align 8
 @ApsiPtr = internal global [16 x double] [double 0x3FB11148FD9FD36F, double 1.666700e-01, double 1.111100e-01, double 6.250000e-02, double 6.250000e-02, double 8.333000e-02, double 8.333000e-02, double 1.250000e-01, double 9.091000e-02, double 9.091000e-02, double 1.111100e-01, double 1.111100e-01, double 9.091000e-02, double 1.666700e-01, double 1.428600e-01, double 3.333300e-01], align 8
 @psiPtr = internal global [16 x double] zeroinitializer, align 8
 @diagPtr = internal global [16 x double] [double 7.692000e-02, double 0x3FB2493C89F40A28, double 5.000000e-01, double 1.250000e-01, double 6.250000e-02, double 8.333000e-02, double 8.333000e-02, double 7.692000e-02, double 1.111100e-01, double 1.666700e-01, double 1.111100e-01, double 1.111100e-01, double 0x3FB2493C89F40A28, double 7.692000e-02, double 1.000000e-01, double 8.333000e-02], align 8
 
 ; Function Attrs: nofree norecurse nosync nounwind uwtable vscale_range(1,16)
 define dso_local i32 @main(i32 %argc, i8** nocapture readnone %argv) local_unnamed_addr #0 {
+;
 ; CHECK-LABEL: @main(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
 ; CHECK-NEXT:    [[PREDICATE_ENTRY:%.*]] = icmp ult <vscale x 2 x i64> [[TMP0]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 16, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
 ; CHECK-NEXT:    [[TMP1:%.*]] = tail call i64 @llvm.vscale.i64()
 ; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i64 [[TMP1]], 1
 ; CHECK-NEXT:    br label [[VECTOR_PH:%.*]]
 ; CHECK:       vector.ph:

 ; CHECK-NEXT:    ret i32 0
 ; CHECK:       for.body8.i:
 ; CHECK-NEXT:    [[INDVARS_IV_I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_I:%.*]], [[FOR_BODY8_I]] ], [ 0, [[VECTOR_BODY]] ]
 ; CHECK-NEXT:    [[ARRAYIDX10_I:%.*]] = getelementptr inbounds [16 x double], [16 x double]* @lowerPtr, i64 0, i64 [[INDVARS_IV_I]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = load double, double* [[ARRAYIDX10_I]], align 8
 ; CHECK-NEXT:    [[ARRAYIDX12_I:%.*]] = getelementptr inbounds [16 x i32], [16 x i32]* @lPtr, i64 0, i64 [[INDVARS_IV_I]]
 ; CHECK-NEXT:    [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12_I]], align 4
 ; CHECK-NEXT:    [[IDXPROM13_I:%.*]] = sext i32 [[TMP13]] to i64
-; CHECK-NEXT:    [[ARRAYIDX14_I:%.*]] = getelementptr inbounds [16 x double], [16 x double]* @psiPtr, i64 0, i64 [[IDXPROM13_I]]
-; CHECK-NEXT:    [[TMP14:%.*]] = load double, double* [[ARRAYIDX14_I]], align 8
-; CHECK-NEXT:    [[MUL15_I:%.*]] = fmul contract double [[TMP12]], [[TMP14]]
+; CHECK-NEXT:    [[MUL15_I:%.*]] = fmul contract double [[TMP12]], 0.000000e+00
 ; CHECK-NEXT:    [[ARRAYIDX17_I:%.*]] = getelementptr inbounds [16 x i32], [16 x i32]* @uPtr, i64 0, i64 [[INDVARS_IV_I]]
-; CHECK-NEXT:    [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX17_I]], align 4
-; CHECK-NEXT:    [[IDXPROM18_I:%.*]] = sext i32 [[TMP15]] to i64
+; CHECK-NEXT:    [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX17_I]], align 4
+; CHECK-NEXT:    [[IDXPROM18_I:%.*]] = sext i32 [[TMP14]] to i64
 ; CHECK-NEXT:    [[ARRAYIDX19_I:%.*]] = getelementptr inbounds [16 x double], [16 x double]* @ApsiPtr, i64 0, i64 [[IDXPROM18_I]]
-; CHECK-NEXT:    [[TMP16:%.*]] = load double, double* [[ARRAYIDX19_I]], align 8
-; CHECK-NEXT:    [[ADD_I:%.*]] = fadd contract double [[MUL15_I]], [[TMP16]]
+; CHECK-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX19_I]], align 8
+; CHECK-NEXT:    [[ADD_I:%.*]] = fadd contract double [[MUL15_I]], [[TMP15]]
 ; CHECK-NEXT:    store double [[ADD_I]], double* [[ARRAYIDX19_I]], align 8
 ; CHECK-NEXT:    [[ARRAYIDX21_I:%.*]] = getelementptr inbounds [16 x double], [16 x double]* @upperPtr, i64 0, i64 [[INDVARS_IV_I]]
-; CHECK-NEXT:    [[TMP17:%.*]] = load double, double* [[ARRAYIDX21_I]], align 8
-; CHECK-NEXT:    [[ARRAYIDX25_I:%.*]] = getelementptr inbounds [16 x double], [16 x double]* @psiPtr, i64 0, i64 [[IDXPROM18_I]]
-; CHECK-NEXT:    [[TMP18:%.*]] = load double, double* [[ARRAYIDX25_I]], align 8
-; CHECK-NEXT:    [[MUL26_I:%.*]] = fmul contract double [[TMP17]], [[TMP18]]
+; CHECK-NEXT:    [[TMP16:%.*]] = load double, double* [[ARRAYIDX21_I]], align 8
+; CHECK-NEXT:    [[MUL26_I:%.*]] = fmul contract double [[TMP16]], 0.000000e+00
 ; CHECK-NEXT:    [[ARRAYIDX30_I:%.*]] = getelementptr inbounds [16 x double], [16 x double]* @ApsiPtr, i64 0, i64 [[IDXPROM13_I]]
-; CHECK-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX30_I]], align 8
-; CHECK-NEXT:    [[ADD31_I:%.*]] = fadd contract double [[TMP19]], [[MUL26_I]]
+; CHECK-NEXT:    [[TMP17:%.*]] = load double, double* [[ARRAYIDX30_I]], align 8
+; CHECK-NEXT:    [[ADD31_I:%.*]] = fadd contract double [[TMP17]], [[MUL26_I]]
 ; CHECK-NEXT:    store double [[ADD31_I]], double* [[ARRAYIDX30_I]], align 8
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_I]] = add nuw nsw i64 [[INDVARS_IV_I]], 1
 ; CHECK-NEXT:    [[EXITCOND_NOT_I:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_I]], 16
 ; CHECK-NEXT:    br i1 [[EXITCOND_NOT_I]], label [[AMUL_EXIT]], label [[FOR_BODY8_I]]
 ; CHECK:       AMUL.exit:
 ; CHECK-NEXT:    br i1 [[CMP]], label [[VECTOR_PH]], label [[FOR_COND_CLEANUP:%.*]]
 ;
 entry: