[AMDGPU] Relax verification of soffset in scalar stores

[rampitec]

Summary

It must use m0 only on GFX8. Later chips can use ang SGPR.

[arsenm]

Should get a verifier test

[rampitec]

Added verifier test.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
   if (shouldReadExec(MI)) {
     if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
       ErrInfo = "VALU instruction does not implicitly read exec mask";
       return false;
     }
   }
 
   if (isSMRD(MI)) {
-    if (MI.mayStore()) {
+    if (MI.mayStore() &&
+        ST.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) {
       // The register offset form of scalar stores may only use m0 as the
       // soffset register.
       const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soffset);
       if (Soff && Soff->getReg() != AMDGPU::M0) {
         ErrInfo = "scalar stores must use m0 as offset register";
         return false;
       }
     }

llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir

+# RUN: not --crash llc -march=amdgcn -mcpu=tonga -run-pass=machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX8-ERR %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=machineverifier -o - %s 2>&1 | FileCheck -check-prefix=GFX9 %s
+
+# GFX8-ERR: *** Bad machine code: scalar stores must use m0 as offset register ***
+# GFX9: S_STORE_DWORD_SGPR
+---
+name:            scalar_store_soffset_sgpr
+body:             |
+  bb.0:
+    S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $sgpr10, 0
+    S_ENDPGM 0
+
+...