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Show First 20 Lines • Show All 4,433 Lines • ▼ Show 20 Lines	bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
if (shouldReadExec(MI)) {		if (shouldReadExec(MI)) {
if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {		if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
ErrInfo = "VALU instruction does not implicitly read exec mask";		ErrInfo = "VALU instruction does not implicitly read exec mask";
return false;		return false;
}		}
}		}

if (isSMRD(MI)) {		if (isSMRD(MI)) {
if (MI.mayStore()) {		if (MI.mayStore() &&
		ST.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) {
// The register offset form of scalar stores may only use m0 as the		// The register offset form of scalar stores may only use m0 as the
// soffset register.		// soffset register.
const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soffset);		const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soffset);
if (Soff && Soff->getReg() != AMDGPU::M0) {		if (Soff && Soff->getReg() != AMDGPU::M0) {
ErrInfo = "scalar stores must use m0 as offset register";		ErrInfo = "scalar stores must use m0 as offset register";
return false;		return false;
}		}
}		}
▲ Show 20 Lines • Show All 4,018 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir

				# RUN: not --crash llc -march=amdgcn -mcpu=tonga -run-pass=machineverifier -o /dev/null %s 2>&1 \| FileCheck -check-prefix=GFX8-ERR %s
				# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=machineverifier -o - %s 2>&1 \| FileCheck -check-prefix=GFX9 %s

				# GFX8-ERR: * Bad machine code: scalar stores must use m0 as offset register *
				# GFX9: S_STORE_DWORD_SGPR
				---
				name: scalar_store_soffset_sgpr
				body: \|
				bb.0:
				S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $sgpr10, 0
				S_ENDPGM 0

				...