[SCEV] Fix isImpliedViaMerge() with values from previous iteration (PR56242)

[nikic]

Summary

When trying to prove an implied condition on a phi by proving it for all incoming values, we need to be careful about values coming from a backedge, as these may refer to a previous loop iteration. A variant of this issue was fixed in D101829, but the dominance condition used there isn't quite right: It checks that the value dominates the incoming block, which doesn't exclude backedges (values defined in a loop will usually dominate the loop latch, which is the incoming block of the backedge).

Instead, we should be checking for domination of the phi block. Any values defined inside the loop will not dominate the loop header header phi.

Fixes https://github.com/llvm/llvm-project/issues/56242.

[nikic]

llvm/test/Transforms/IRCE/decrementing-loop.ll

222

This just restores the pre-D101829 state of the test.

[nikic]

Ping

[fhahn]

LGTM, thanks!

llvm/lib/Analysis/ScalarEvolution.cpp

if (RPhi && RPhi->getParent() == LBB) {
     // different from LBB.
     for (const BasicBlock *IncBB : predecessors(LBB)) {
       // Check that RHS is available in this block.
       if (!dominates(RHS, IncBB))
         return false;
       const SCEV *L = getSCEV(LPhi->getIncomingValueForBlock(IncBB));
       // Make sure L does not refer to a value from a potentially previous
       // iteration of a loop.
-      if (!properlyDominates(L, IncBB))
+      if (!properlyDominates(L, LBB))
         return false;
       if (!ProvedEasily(L, RHS))
         return false;
     }
   }
   return true;
 }
 

llvm/test/Transforms/IRCE/decrementing-loop.ll

 
 out.of.bounds:
   ret void
 
 exit:
   ret void
 }
 
-; TODO: we need to be more careful when trying to look through phi nodes in
-; cycles, because the condition to prove may reference the previous value of
-; the phi. So we currently fail to optimize this case.
 ; Check that we can figure out that IV is non-negative via implication through
 ; two Phi nodes, one being AddRec.
 define void @test_05(i32* %a, i32* %a_len_ptr, i1 %cond) {
 
 ; CHECK-LABEL: test_05
-; CHECK: entry:
-; CHECK:   br label %merge
-; CHECK-NOT: mainloop
+; CHECK:       mainloop:
+; CHECK-NEXT:    br label %loop
+; CHECK:       loop:
+; CHECK:         br i1 true, label %in.bounds, label %out.of.bounds
+; CHECK:       loop.preloop:
 
  entry:
   %len.a = load i32, i32* %a_len_ptr, !range !0
   %len.minus.one = sub nsw i32 %len.a, 1
   %len.plus.one = add nsw i32 %len.a, 1
   %len.minus.two = sub nsw i32 %len.a, 2
   br label %merge
 

llvm/test/Transforms/IndVarSimplify/pr56242.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -indvars < %s | FileCheck %s
 
 declare void @use(i1)
 
 define void @test(ptr %arr) {
 ; CHECK-LABEL: @test(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
 ; CHECK:       loop.header:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[IV_INC:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[PREV:%.*]] = phi i32 [ [[V:%.*]], [[LOOP_LATCH]] ], [ 0, [[ENTRY]] ]
 ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr inbounds i32, ptr [[ARR:%.*]], i64 [[IV]]
-; CHECK-NEXT:    [[V:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT:    [[V]] = load i32, ptr [[PTR]], align 4
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[V]], 0
 ; CHECK-NEXT:    br i1 [[CMP1]], label [[IF:%.*]], label [[LOOP_LATCH]]
 ; CHECK:       if:
-; CHECK-NEXT:    call void @use(i1 false)
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[PREV]], 0
+; CHECK-NEXT:    call void @use(i1 [[CMP2]])
 ; CHECK-NEXT:    br label [[LOOP_LATCH]]
 ; CHECK:       loop.latch:
 ; CHECK-NEXT:    [[IV_INC]] = add nuw nsw i64 [[IV]], 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i64 [[IV_INC]], 16
 ; CHECK-NEXT:    br i1 [[CMP]], label [[LOOP_HEADER]], label [[EXIT:%.*]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;